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0e6be855a9
Add the PLL clock controller dt-bindings for Amlogic C3 SoC family. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Co-developed-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20240522082727.3029656-2-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
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* Author: Chuan Liu <chuan.liu@amlogic.com>
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
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#define CLKID_FCLK_50M_EN 0
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#define CLKID_FCLK_50M 1
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#define CLKID_FCLK_DIV2_DIV 2
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#define CLKID_FCLK_DIV2 3
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#define CLKID_FCLK_DIV2P5_DIV 4
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#define CLKID_FCLK_DIV2P5 5
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#define CLKID_FCLK_DIV3_DIV 6
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#define CLKID_FCLK_DIV3 7
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#define CLKID_FCLK_DIV4_DIV 8
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#define CLKID_FCLK_DIV4 9
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#define CLKID_FCLK_DIV5_DIV 10
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#define CLKID_FCLK_DIV5 11
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#define CLKID_FCLK_DIV7_DIV 12
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#define CLKID_FCLK_DIV7 13
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#define CLKID_GP0_PLL_DCO 14
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#define CLKID_GP0_PLL 15
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#define CLKID_HIFI_PLL_DCO 16
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#define CLKID_HIFI_PLL 17
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#define CLKID_MCLK_PLL_DCO 18
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#define CLKID_MCLK_PLL_OD 19
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#define CLKID_MCLK_PLL 20
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#define CLKID_MCLK0_SEL 21
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#define CLKID_MCLK0_SEL_EN 22
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#define CLKID_MCLK0_DIV 23
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#define CLKID_MCLK0 24
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#define CLKID_MCLK1_SEL 25
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#define CLKID_MCLK1_SEL_EN 26
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#define CLKID_MCLK1_DIV 27
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#define CLKID_MCLK1 28
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
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