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36f257e3b0
When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. Introduce support for handling and logging CXL Protocol errors. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse them to trace FW-First Protocol errors. Since the CXL code is required to be called from process context and GHES is in interrupt context, use workqueues for processing. Similar to CXL CPER event handling, use kfifo to handle errors as it simplifies queue processing by providing lock free fifo operations. Add the ability for the CXL sub-system to register a workqueue to process CXL CPER protocol errors. [DJ: return cxl_cper_register_prot_err_work() directly in cxl_ras_init()] Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20250310223839.31342-2-Smita.KoralahalliChannabasappa@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
288 lines
6.3 KiB
C
288 lines
6.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2023 Intel Corporation. */
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#ifndef _LINUX_CXL_EVENT_H
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#define _LINUX_CXL_EVENT_H
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#include <linux/types.h>
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#include <linux/uuid.h>
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#include <linux/workqueue_types.h>
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/*
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* Common Event Record Format
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_hdr {
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u8 length;
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u8 flags[3];
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__le16 handle;
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__le16 related_handle;
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__le64 timestamp;
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u8 maint_op_class;
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u8 maint_op_sub_class;
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u8 reserved[14];
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} __packed;
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struct cxl_event_media_hdr {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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/*
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* The meaning of Validity Flags from bit 2 is
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* different across DRAM and General Media records
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*/
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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} __packed;
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#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
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struct cxl_event_generic {
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struct cxl_event_record_hdr hdr;
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u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
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} __packed;
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/*
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* General Media Event Record
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* CXL rev 3.1 Section 8.2.9.2.1.1; Table 8-45
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*/
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#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
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struct cxl_event_gen_media {
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struct cxl_event_media_hdr media_hdr;
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u8 device[3];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 cme_threshold_ev_flags;
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u8 cme_count[3];
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u8 sub_type;
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u8 reserved[41];
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} __packed;
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/*
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* DRAM Event Record - DER
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* CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
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*/
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#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
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struct cxl_event_dram {
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struct cxl_event_media_hdr media_hdr;
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u8 nibble_mask[3];
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u8 bank_group;
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u8 bank;
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u8 row[3];
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u8 column[2];
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u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 sub_channel;
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u8 cme_threshold_ev_flags;
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u8 cvme_count[3];
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u8 sub_type;
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u8 reserved;
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} __packed;
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/*
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* Get Health Info Record
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* CXL rev 3.1 section 8.2.9.9.3.1; Table 8-133
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*/
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struct cxl_get_health_info {
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u8 health_status;
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u8 media_status;
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u8 add_status;
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u8 life_used;
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u8 device_temp[2];
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u8 dirty_shutdown_cnt[4];
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u8 cor_vol_err_cnt[4];
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u8 cor_per_err_cnt[4];
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} __packed;
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/*
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* Memory Module Event Record
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* CXL rev 3.1 section 8.2.9.2.1.3; Table 8-47
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*/
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struct cxl_event_mem_module {
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struct cxl_event_record_hdr hdr;
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u8 event_type;
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struct cxl_get_health_info info;
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u8 validity_flags[2];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 event_sub_type;
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u8 reserved[0x2a];
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} __packed;
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union cxl_event {
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struct cxl_event_generic generic;
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struct cxl_event_gen_media gen_media;
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struct cxl_event_dram dram;
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struct cxl_event_mem_module mem_module;
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/* dram & gen_media event header */
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struct cxl_event_media_hdr media_hdr;
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} __packed;
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/*
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* Common Event Record Format; in event logs
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_raw {
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uuid_t id;
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union cxl_event event;
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} __packed;
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enum cxl_event_type {
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CXL_CPER_EVENT_GENERIC,
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CXL_CPER_EVENT_GEN_MEDIA,
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CXL_CPER_EVENT_DRAM,
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CXL_CPER_EVENT_MEM_MODULE,
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};
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#define CPER_CXL_DEVICE_ID_VALID BIT(0)
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#define CPER_CXL_DEVICE_SN_VALID BIT(1)
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#define CPER_CXL_COMP_EVENT_LOG_VALID BIT(2)
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struct cxl_cper_event_rec {
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struct {
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u32 length;
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u64 validation_bits;
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struct cper_cxl_event_devid {
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u16 vendor_id;
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u16 device_id;
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u8 func_num;
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u8 device_num;
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u8 bus_num;
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u16 segment_num;
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u16 slot_num; /* bits 2:0 reserved */
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u8 reserved;
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} __packed device_id;
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struct cper_cxl_event_sn {
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u32 lower_dw;
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u32 upper_dw;
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} __packed dev_serial_num;
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} __packed hdr;
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union cxl_event event;
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} __packed;
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struct cxl_cper_work_data {
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enum cxl_event_type event_type;
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struct cxl_cper_event_rec rec;
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};
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#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0)
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#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1)
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#define PROT_ERR_VALID_DEVICE_ID BIT_ULL(2)
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#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3)
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#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4)
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#define PROT_ERR_VALID_DVSEC BIT_ULL(5)
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#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6)
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/*
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* The layout of the enumeration and the values matches CXL Agent Type
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* field in the UEFI 2.10 Section N.2.13,
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*/
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enum {
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RCD, /* Restricted CXL Device */
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RCH_DP, /* Restricted CXL Host Downstream Port */
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DEVICE, /* CXL Device */
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LD, /* CXL Logical Device */
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FMLD, /* CXL Fabric Manager managed Logical Device */
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RP, /* CXL Root Port */
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DSP, /* CXL Downstream Switch Port */
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USP, /* CXL Upstream Switch Port */
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};
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#pragma pack(1)
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/* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */
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struct cxl_cper_sec_prot_err {
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u64 valid_bits;
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u8 agent_type;
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u8 reserved[7];
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/*
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* Except for RCH Downstream Port, all the remaining CXL Agent
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* types are uniquely identified by the PCIe compatible SBDF number.
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*/
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union {
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u64 rcrb_base_addr;
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struct {
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u8 function;
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u8 device;
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u8 bus;
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u16 segment;
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u8 reserved_1[3];
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};
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} agent_addr;
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struct {
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u16 vendor_id;
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u16 device_id;
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u16 subsystem_vendor_id;
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u16 subsystem_id;
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u8 class_code[2];
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u16 slot;
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u8 reserved_1[4];
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} device_id;
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struct {
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u32 lower_dw;
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u32 upper_dw;
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} dev_serial_num;
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u8 capability[60];
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u16 dvsec_len;
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u16 err_len;
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u8 reserved_2[4];
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};
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#pragma pack()
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/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */
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struct cxl_ras_capability_regs {
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u32 uncor_status;
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u32 uncor_mask;
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u32 uncor_severity;
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u32 cor_status;
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u32 cor_mask;
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u32 cap_control;
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u32 header_log[16];
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};
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struct cxl_cper_prot_err_work_data {
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struct cxl_cper_sec_prot_err prot_err;
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struct cxl_ras_capability_regs ras_cap;
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int severity;
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};
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#ifdef CONFIG_ACPI_APEI_GHES
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int cxl_cper_register_work(struct work_struct *work);
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int cxl_cper_unregister_work(struct work_struct *work);
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int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd);
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int cxl_cper_register_prot_err_work(struct work_struct *work);
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int cxl_cper_unregister_prot_err_work(struct work_struct *work);
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int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd);
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#else
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static inline int cxl_cper_register_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_unregister_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd)
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{
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return 0;
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}
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static inline int cxl_cper_register_prot_err_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_unregister_prot_err_work(struct work_struct *work)
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{
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return 0;
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}
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static inline int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd)
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{
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return 0;
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}
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#endif
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#endif /* _LINUX_CXL_EVENT_H */
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