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0666e3fe95
Define a new RSCI port type, and the RSCI 32 bits registers set. The RZ/T2H SCI has a a fifo, and a quite different set of registers from the original SH SCI ones. DMA is not supported yet. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250630202323.279809-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
175 lines
4.3 KiB
C
175 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SH_SCI_COMMON_H__
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#define __SH_SCI_COMMON_H__
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#include <linux/serial_core.h>
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/* Private port IDs */
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enum SCI_PORT_TYPE {
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SCI_PORT_RSCI = BIT(7) | 0,
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};
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enum SCI_CLKS {
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SCI_FCK, /* Functional Clock */
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SCI_SCK, /* Optional External Clock */
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SCI_BRG_INT, /* Optional BRG Internal Clock Source */
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SCI_SCIF_CLK, /* Optional BRG External Clock Source */
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SCI_NUM_CLKS
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};
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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SCIx_RXI_IRQ,
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SCIx_TXI_IRQ,
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SCIx_BRI_IRQ,
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SCIx_DRI_IRQ,
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SCIx_TEI_IRQ,
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SCIx_NR_IRQS,
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SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
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};
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/* Bit x set means sampling rate x + 1 is supported */
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#define SCI_SR(x) BIT((x) - 1)
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#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
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void sci_release_port(struct uart_port *port);
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int sci_request_port(struct uart_port *port);
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void sci_config_port(struct uart_port *port, int flags);
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int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
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void sci_pm(struct uart_port *port, unsigned int state,
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unsigned int oldstate);
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struct plat_sci_reg {
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u8 offset;
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u8 size;
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};
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struct sci_port_params_bits {
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unsigned int rxtx_enable;
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unsigned int te_clear;
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unsigned int poll_sent_bits;
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};
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struct sci_common_regs {
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unsigned int status;
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unsigned int control;
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};
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/* The actual number of needed registers. This is used by sci only */
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#define SCI_NR_REGS 20
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struct sci_port_params {
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const struct plat_sci_reg regs[SCI_NR_REGS];
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const struct sci_common_regs *common_regs;
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const struct sci_port_params_bits *param_bits;
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unsigned int fifosize;
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unsigned int overrun_reg;
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unsigned int overrun_mask;
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unsigned int sampling_rate_mask;
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unsigned int error_mask;
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unsigned int error_clear;
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};
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struct sci_port_ops {
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u32 (*read_reg)(struct uart_port *port, int reg);
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void (*write_reg)(struct uart_port *port, int reg, int value);
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void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
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void (*transmit_chars)(struct uart_port *port);
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void (*receive_chars)(struct uart_port *port);
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void (*poll_put_char)(struct uart_port *port, unsigned char c);
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int (*set_rtrg)(struct uart_port *port, int rx_trig);
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int (*rtrg_enabled)(struct uart_port *port);
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void (*shutdown_complete)(struct uart_port *port);
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void (*prepare_console_write)(struct uart_port *port, u32 ctrl);
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void (*console_save)(struct uart_port *port);
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void (*console_restore)(struct uart_port *port);
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size_t (*suspend_regs_size)(void);
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};
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struct sci_of_data {
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const struct sci_port_params *params;
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const struct uart_ops *uart_ops;
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const struct sci_port_ops *ops;
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unsigned short regtype;
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unsigned short type;
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};
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struct sci_port {
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struct uart_port port;
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/* Platform configuration */
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const struct sci_port_params *params;
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const struct plat_sci_port *cfg;
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unsigned int sampling_rate_mask;
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resource_size_t reg_size;
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struct mctrl_gpios *gpios;
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/* Clocks */
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struct clk *clks[SCI_NUM_CLKS];
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unsigned long clk_rates[SCI_NUM_CLKS];
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int irqs[SCIx_NR_IRQS];
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char *irqstr[SCIx_NR_IRQS];
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struct dma_chan *chan_tx;
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struct dma_chan *chan_rx;
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struct reset_control *rstc;
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struct sci_suspend_regs *suspend_regs;
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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struct dma_chan *chan_tx_saved;
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struct dma_chan *chan_rx_saved;
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dma_cookie_t cookie_tx;
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dma_cookie_t cookie_rx[2];
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dma_cookie_t active_rx;
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dma_addr_t tx_dma_addr;
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unsigned int tx_dma_len;
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struct scatterlist sg_rx[2];
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void *rx_buf[2];
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size_t buf_len_rx;
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struct work_struct work_tx;
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struct hrtimer rx_timer;
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unsigned int rx_timeout; /* microseconds */
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#endif
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unsigned int rx_frame;
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int rx_trigger;
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struct timer_list rx_fifo_timer;
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int rx_fifo_timeout;
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u16 hscif_tot;
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u8 type;
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u8 regtype;
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const struct sci_port_ops *ops;
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bool has_rtscts;
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bool autorts;
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bool tx_occurred;
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};
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#define to_sci_port(uart) container_of((uart), struct sci_port, port)
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void sci_port_disable(struct sci_port *sci_port);
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void sci_port_enable(struct sci_port *sci_port);
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int sci_startup(struct uart_port *port);
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void sci_shutdown(struct uart_port *port);
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#define min_sr(_port) ffs((_port)->sampling_rate_mask)
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#define max_sr(_port) fls((_port)->sampling_rate_mask)
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#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
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int __init scix_early_console_setup(struct earlycon_device *device, const struct sci_of_data *data);
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#endif
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#endif /* __SH_SCI_COMMON_H__ */
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