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efef7f184f
For historic reasons there are some TSC-related functions in the
<asm/msr.h> header, even though there's an <asm/tsc.h> header.
To facilitate the relocation of rdtsc{,_ordered}() from <asm/msr.h>
to <asm/tsc.h> and to eventually eliminate the inclusion of
<asm/msr.h> in <asm/tsc.h>, add an explicit <asm/msr.h> dependency
to the source files that reference definitions from <asm/msr.h>.
[ mingo: Clarified the changelog. ]
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Uros Bizjak <ubizjak@gmail.com>
Link: https://lore.kernel.org/r/20250501054241.1245648-1-xin@zytor.com
125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cooling device driver that activates the processor throttling by
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* programming the TCC Offset register.
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* Copyright (c) 2021, Intel Corporation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/device.h>
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#include <linux/intel_tcc.h>
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#include <linux/module.h>
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#include <linux/thermal.h>
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#include <asm/cpu_device_id.h>
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#include <asm/msr.h>
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#define TCC_PROGRAMMABLE BIT(30)
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#define TCC_LOCKED BIT(31)
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static struct thermal_cooling_device *tcc_cdev;
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static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long
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*state)
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{
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*state = intel_tcc_get_offset_mask();
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return 0;
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}
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static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long
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*state)
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{
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int offset = intel_tcc_get_offset(-1);
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if (offset < 0)
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return offset;
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*state = offset;
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return 0;
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}
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static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long
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state)
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{
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return intel_tcc_set_offset(-1, (int)state);
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}
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static const struct thermal_cooling_device_ops tcc_cooling_ops = {
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.get_max_state = tcc_get_max_state,
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.get_cur_state = tcc_get_cur_state,
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.set_cur_state = tcc_set_cur_state,
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};
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static const struct x86_cpu_id tcc_ids[] __initconst = {
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X86_MATCH_VFM(INTEL_SKYLAKE, NULL),
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X86_MATCH_VFM(INTEL_SKYLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_KABYLAKE, NULL),
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X86_MATCH_VFM(INTEL_KABYLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ICELAKE, NULL),
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X86_MATCH_VFM(INTEL_ICELAKE_L, NULL),
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X86_MATCH_VFM(INTEL_TIGERLAKE, NULL),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_COMETLAKE, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_S, NULL),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, tcc_ids);
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static int __init tcc_cooling_init(void)
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{
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int ret;
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u64 val;
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const struct x86_cpu_id *id;
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int err;
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id = x86_match_cpu(tcc_ids);
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if (!id)
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return -ENODEV;
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err = rdmsrq_safe(MSR_PLATFORM_INFO, &val);
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if (err)
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return err;
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if (!(val & TCC_PROGRAMMABLE))
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return -ENODEV;
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err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
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if (err)
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return err;
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if (val & TCC_LOCKED) {
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pr_info("TCC Offset locked\n");
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return -ENODEV;
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}
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pr_info("Programmable TCC Offset detected\n");
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tcc_cdev =
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thermal_cooling_device_register("TCC Offset", NULL,
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&tcc_cooling_ops);
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if (IS_ERR(tcc_cdev)) {
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ret = PTR_ERR(tcc_cdev);
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return ret;
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}
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return 0;
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}
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module_init(tcc_cooling_init)
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static void __exit tcc_cooling_exit(void)
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{
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thermal_cooling_device_unregister(tcc_cdev);
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}
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module_exit(tcc_cooling_exit)
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MODULE_IMPORT_NS("INTEL_TCC");
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MODULE_DESCRIPTION("TCC offset cooling device Driver");
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MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
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MODULE_LICENSE("GPL v2");
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