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e1f3f5be9e
ACE3 introduced microphone privacy and along this feature it adds a new register in vendor specific SHIM to control and status reporting. The control of mic privacy via the SHIM register is only to enable the interrupt generation via soundwire, but not handled by the soundwire code as the mic privacy is not a feature of the soundwire IP. On the other hand, printing the register value brings value for debugging, so add a new flag to allow this conditionally. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20250430074714.94000-2-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/* Copyright(c) 2015-17 Intel Corporation. */
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#ifndef __SDW_INTEL_LOCAL_H
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#define __SDW_INTEL_LOCAL_H
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struct hdac_bus;
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/**
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* struct sdw_intel_link_res - Soundwire Intel link resource structure,
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* typically populated by the controller driver.
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* @hw_ops: platform-specific ops
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* @mmio_base: mmio base of SoundWire registers
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* @registers: Link IO registers base
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* @ip_offset: offset for MCP_IP registers
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* @shim: Audio shim pointer
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* @shim_vs: Audio vendor-specific shim pointer
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* @alh: ALH (Audio Link Hub) pointer
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* @irq: Interrupt line
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* @ops: Shim callback ops
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* @dev: device implementing hw_params and free callbacks
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* @shim_lock: mutex to handle access to shared SHIM registers
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* @shim_mask: global pointer to check SHIM register initialization
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* @clock_stop_quirks: mask defining requested behavior on pm_suspend
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* @mic_privacy: ACE version supports microphone privacy
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* @link_mask: global mask needed for power-up/down sequences
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* @cdns: Cadence master descriptor
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* @list: used to walk-through all masters exposed by the same controller
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* @hbus: hdac_bus pointer, needed for power management
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*/
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struct sdw_intel_link_res {
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const struct sdw_intel_hw_ops *hw_ops;
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void __iomem *mmio_base; /* not strictly needed, useful for debug */
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void __iomem *registers;
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u32 ip_offset;
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void __iomem *shim;
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void __iomem *shim_vs;
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void __iomem *alh;
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int irq;
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const struct sdw_intel_ops *ops;
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struct device *dev;
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struct mutex *shim_lock; /* protect shared registers */
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u32 *shim_mask;
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u32 clock_stop_quirks;
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bool mic_privacy;
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u32 link_mask;
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struct sdw_cdns *cdns;
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struct list_head list;
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struct hdac_bus *hbus;
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};
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/**
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* struct sdw_intel_bpt - SoundWire Intel BPT context
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* @bpt_tx_stream: BPT TX stream
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* @dmab_tx_bdl: BPT TX buffer descriptor list
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* @bpt_rx_stream: BPT RX stream
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* @dmab_rx_bdl: BPT RX buffer descriptor list
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* @pdi0_buffer_size: PDI0 buffer size
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* @pdi1_buffer_size: PDI1 buffer size
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* @num_frames: number of frames
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* @data_per_frame: data per frame
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*/
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struct sdw_intel_bpt {
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struct hdac_ext_stream *bpt_tx_stream;
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struct snd_dma_buffer dmab_tx_bdl;
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struct hdac_ext_stream *bpt_rx_stream;
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struct snd_dma_buffer dmab_rx_bdl;
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unsigned int pdi0_buffer_size;
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unsigned int pdi1_buffer_size;
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unsigned int num_frames;
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unsigned int data_per_frame;
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};
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struct sdw_intel {
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struct sdw_cdns cdns;
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int instance;
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struct sdw_intel_link_res *link_res;
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bool startup_done;
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struct sdw_intel_bpt bpt_ctx;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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struct sdw_intel_prop {
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u16 clde;
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u16 doaise2;
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u16 dodse2;
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u16 clds;
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u16 clss;
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u16 doaise;
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u16 doais;
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u16 dodse;
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u16 dods;
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};
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enum intel_pdi_type {
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INTEL_PDI_IN = 0,
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INTEL_PDI_OUT = 1,
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INTEL_PDI_BD = 2,
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};
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/*
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* Read, write helpers for HW registers
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*/
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static inline int intel_readl(void __iomem *base, int offset)
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{
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return readl(base + offset);
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}
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static inline void intel_writel(void __iomem *base, int offset, int value)
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{
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writel(value, base + offset);
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}
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static inline u16 intel_readw(void __iomem *base, int offset)
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{
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return readw(base + offset);
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}
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static inline void intel_writew(void __iomem *base, int offset, u16 value)
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{
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writew(value, base + offset);
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}
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#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
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#define INTEL_MASTER_RESET_ITERATIONS 10
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#define SDW_INTEL_DELAYED_ENUMERATION_MS 100
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#define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \
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(sdw)->link_res->hw_ops->cb)
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#define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb)
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#ifdef CONFIG_DEBUG_FS
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void intel_ace2x_debugfs_init(struct sdw_intel *sdw);
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void intel_ace2x_debugfs_exit(struct sdw_intel *sdw);
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#else
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static inline void intel_ace2x_debugfs_init(struct sdw_intel *sdw) {}
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static inline void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) {}
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#endif
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static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init))
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SDW_INTEL_OPS(sdw, debugfs_init)(sdw);
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}
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static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit))
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SDW_INTEL_OPS(sdw, debugfs_exit)(sdw);
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}
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static inline int sdw_intel_register_dai(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, register_dai))
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return SDW_INTEL_OPS(sdw, register_dai)(sdw);
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return -ENOTSUPP;
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}
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static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop))
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SDW_INTEL_OPS(sdw, check_clock_stop)(sdw);
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}
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static inline int sdw_intel_start_bus(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, start_bus))
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return SDW_INTEL_OPS(sdw, start_bus)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset))
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return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop))
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return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, stop_bus))
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return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_link_power_up(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, link_power_up))
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return SDW_INTEL_OPS(sdw, link_power_up)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_link_power_down(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, link_power_down))
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return SDW_INTEL_OPS(sdw, link_power_down)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake))
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return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw);
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return -ENOTSUPP;
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}
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static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, shim_wake))
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SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable);
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}
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static inline void sdw_intel_sync_arm(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, sync_arm))
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SDW_INTEL_OPS(sdw, sync_arm)(sdw);
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}
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static inline int sdw_intel_sync_go_unlocked(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, sync_go_unlocked))
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return SDW_INTEL_OPS(sdw, sync_go_unlocked)(sdw);
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return -ENOTSUPP;
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}
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static inline int sdw_intel_sync_go(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, sync_go))
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return SDW_INTEL_OPS(sdw, sync_go)(sdw);
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return -ENOTSUPP;
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}
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static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, sync_check_cmdsync_unlocked))
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return SDW_INTEL_OPS(sdw, sync_check_cmdsync_unlocked)(sdw);
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return false;
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}
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static inline int sdw_intel_get_link_count(struct sdw_intel *sdw)
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{
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if (SDW_INTEL_CHECK_OPS(sdw, get_link_count))
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return SDW_INTEL_OPS(sdw, get_link_count)(sdw);
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return 4; /* default on older generations */
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}
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/* common bus management */
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int intel_start_bus(struct sdw_intel *sdw);
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int intel_start_bus_after_reset(struct sdw_intel *sdw);
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void intel_check_clock_stop(struct sdw_intel *sdw);
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int intel_start_bus_after_clock_stop(struct sdw_intel *sdw);
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int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop);
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/* common bank switch routines */
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int intel_pre_bank_switch(struct sdw_intel *sdw);
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int intel_post_bank_switch(struct sdw_intel *sdw);
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#endif /* __SDW_INTEL_LOCAL_H */
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