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e3f1fe9898
To improve the code organization and readability, move the macros and structures from the AMD PMC driver to the PMC header file. Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20250305142615.410178-2-Shyam-sundar.S-k@amd.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
173 lines
4.4 KiB
C
173 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* AMD SoC Power Management Controller Driver
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*
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* Copyright (c) 2023, Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Author: Mario Limonciello <mario.limonciello@amd.com>
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*/
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#ifndef PMC_H
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#define PMC_H
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#include <linux/types.h>
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#include <linux/mutex.h>
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/* SMU communication registers */
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#define AMD_PMC_REGISTER_RESPONSE 0x980
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#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
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/* PMC Scratch Registers */
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#define AMD_PMC_SCRATCH_REG_CZN 0x94
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#define AMD_PMC_SCRATCH_REG_YC 0xD14
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#define AMD_PMC_SCRATCH_REG_1AH 0xF14
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/* STB Registers */
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#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
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#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
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#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
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/* Base address of SMU for mapping physical address to virtual address */
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#define AMD_PMC_MAPPING_SIZE 0x01000
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#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
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#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
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#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
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#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
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#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
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/* SMU Response Codes */
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#define AMD_PMC_RESULT_OK 0x01
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#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
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#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
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#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
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#define AMD_PMC_RESULT_FAILED 0xFF
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/* FCH SSC Registers */
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#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
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#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
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#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
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#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
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#define FCH_SSC_MAPPING_SIZE 0x800
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#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
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#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
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/* SMU Message Definations */
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#define SMU_MSG_GETSMUVERSION 0x02
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#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
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#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
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#define SMU_MSG_LOG_START 0x06
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#define SMU_MSG_LOG_RESET 0x07
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#define SMU_MSG_LOG_DUMP_DATA 0x08
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#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
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#define PMC_MSG_DELAY_MIN_US 50
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#define RESPONSE_REGISTER_LOOP_MAX 20000
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#define DELAY_MIN_US 2000
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#define DELAY_MAX_US 3000
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enum s2d_msg_port {
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MSG_PORT_PMC,
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MSG_PORT_S2D,
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};
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struct amd_mp2_dev {
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void __iomem *mmio;
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void __iomem *vslbase;
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void *stbdata;
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void *devres_gid;
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struct pci_dev *pdev;
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dma_addr_t dma_addr;
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int stb_len;
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bool is_stb_data;
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};
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struct stb_arg {
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u32 s2d_msg_id;
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u32 msg;
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u32 arg;
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u32 resp;
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};
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struct amd_pmc_dev {
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void __iomem *regbase;
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void __iomem *smu_virt_addr;
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void __iomem *stb_virt_addr;
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void __iomem *fch_virt_addr;
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u32 base_addr;
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u32 cpu_id;
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u32 dram_size;
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u32 active_ips;
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const struct amd_pmc_bit_map *ips_ptr;
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u32 num_ips;
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u32 smu_msg;
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/* SMU version information */
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u8 smu_program;
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u8 major;
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u8 minor;
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u8 rev;
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u8 msg_port;
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struct device *dev;
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struct pci_dev *rdev;
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struct mutex lock; /* generic mutex lock */
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struct dentry *dbgfs_dir;
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struct quirk_entry *quirks;
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bool disable_8042_wakeup;
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struct amd_mp2_dev *mp2;
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struct stb_arg stb_arg;
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};
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struct amd_pmc_bit_map {
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const char *name;
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u32 bit_mask;
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};
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struct smu_metrics {
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u32 table_version;
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u32 hint_count;
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u32 s0i3_last_entry_status;
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u32 timein_s0i2;
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u64 timeentering_s0i3_lastcapture;
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u64 timeentering_s0i3_totaltime;
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u64 timeto_resume_to_os_lastcapture;
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u64 timeto_resume_to_os_totaltime;
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u64 timein_s0i3_lastcapture;
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u64 timein_s0i3_totaltime;
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u64 timein_swdrips_lastcapture;
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u64 timein_swdrips_totaltime;
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u64 timecondition_notmet_lastcapture[32];
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u64 timecondition_notmet_totaltime[32];
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} __packed;
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enum amd_pmc_def {
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MSG_TEST = 0x01,
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MSG_OS_HINT_PCO,
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MSG_OS_HINT_RN,
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};
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void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);
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void amd_pmc_quirks_init(struct amd_pmc_dev *dev);
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void amd_mp2_stb_init(struct amd_pmc_dev *dev);
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void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
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/* List of supported CPU ids */
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#define AMD_CPU_ID_RV 0x15D0
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#define AMD_CPU_ID_RN 0x1630
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#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
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#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
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#define AMD_CPU_ID_YC 0x14B5
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#define AMD_CPU_ID_CB 0x14D8
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#define AMD_CPU_ID_PS 0x14E8
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#define AMD_CPU_ID_SP 0x14A4
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#define AMD_CPU_ID_SHP 0x153A
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#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
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#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
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#define PCI_DEVICE_ID_AMD_MP2_STB 0x172c
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int amd_stb_s2d_init(struct amd_pmc_dev *dev);
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int amd_stb_read(struct amd_pmc_dev *dev, u32 *buf);
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int amd_stb_write(struct amd_pmc_dev *dev, u32 data);
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int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
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#endif /* PMC_H */
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