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03aa45d6c6
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_H_
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#define QCOM_PHY_QMP_H_
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#include "phy-qcom-qmp-qserdes-com.h"
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#include "phy-qcom-qmp-qserdes-txrx.h"
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#include "phy-qcom-qmp-qserdes-com-v3.h"
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#include "phy-qcom-qmp-qserdes-txrx-v3.h"
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#include "phy-qcom-qmp-qserdes-com-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
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#include "phy-qcom-qmp-qserdes-com-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
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#include "phy-qcom-qmp-qserdes-com-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v5.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
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#include "phy-qcom-qmp-qserdes-com-v7.h"
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#include "phy-qcom-qmp-qserdes-txrx-v7.h"
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#include "phy-qcom-qmp-qserdes-com-v8.h"
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#include "phy-qcom-qmp-qserdes-txrx-v8.h"
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#include "phy-qcom-qmp-qserdes-pll.h"
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#include "phy-qcom-qmp-pcs-v2.h"
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#include "phy-qcom-qmp-pcs-v3.h"
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#include "phy-qcom-qmp-pcs-v4.h"
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#include "phy-qcom-qmp-pcs-v4_20.h"
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#include "phy-qcom-qmp-pcs-v5.h"
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#include "phy-qcom-qmp-pcs-v5_20.h"
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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6-n4.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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#include "phy-qcom-qmp-pcs-v7.h"
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#include "phy-qcom-qmp-pcs-v8.h"
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/* QPHY_SW_RESET bit */
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#define SW_RESET BIT(0)
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/* QPHY_POWER_DOWN_CONTROL */
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#define SW_PWRDN BIT(0)
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#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
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/* QPHY_START_CONTROL bits */
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#define SERDES_START BIT(0)
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#define PCS_START BIT(1)
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/* QPHY_PCS_STATUS bit */
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#define PHYSTATUS BIT(6)
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#define PHYSTATUS_4_20 BIT(7)
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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#define ARCVR_DTCT_EN BIT(0)
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#define ALFPS_DTCT_EN BIT(1)
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#define ARCVR_DTCT_EVENT_SEL BIT(4)
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/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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#define IRQ_CLEAR BIT(0)
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/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
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#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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#endif
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