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b02cc9a176
Add SM8750 specific register layout and table configs. The serdes TX RX register offset has changed for SM8750 and hence keep UFS specific serdes offsets in a dedicated header file. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Co-developed-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-2-0dfdd6823161@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
67 lines
3.3 KiB
C
67 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V7_H_
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#define QSERDES_UFS_V7_TX_RES_CODE_LANE_TX 0x28
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#define QSERDES_UFS_V7_TX_RES_CODE_LANE_RX 0x2c
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#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_UFS_V7_TX_LANE_MODE_1 0x7c
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#define QSERDES_UFS_V7_TX_FR_DCC_CTRL 0x108
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#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
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#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
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#define QSERDES_UFS_V7_RX_UCDR_SO_SATURATION 0x28
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#define QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
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#define QSERDES_UFS_V7_RX_UCDR_PI_CTRL1 0x58
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#define QSERDES_UFS_V7_RX_TERM_BW_CTRL0 0xc4
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#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2 0xd4
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#define QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4 0xdc
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#define QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4 0xf0
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#define QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS 0xf4
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#define QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL 0x178
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#define QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4 0x1b4
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#define QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1cc
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#define QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3 0x1d4
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#define QSERDES_UFS_V7_RX_INTERFACE_MODE 0x1f0
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0 0x218
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1 0x21C
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2 0x220
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3 0x224
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4 0x228
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6 0x230
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#define QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7 0x234
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#define QSERDES_UFS_V7_RX_MODE_RATE2_B3 0x248
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#define QSERDES_UFS_V7_RX_MODE_RATE2_B6 0x254
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#define QSERDES_UFS_V7_RX_MODE_RATE2_B7 0x258
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B0 0x260
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B1 0x264
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B2 0x268
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B3 0x26c
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B4 0x270
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B5 0x274
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B7 0x27c
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#define QSERDES_UFS_V7_RX_MODE_RATE3_B8 0x280
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0 0x284
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1 0x288
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2 0x28c
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3 0x290
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4 0x294
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5 0x298
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6 0x29c
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7 0x2a0
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0 0x2a8
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1 0x2ac
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2 0x2b0
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3 0x2b4
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4 0x2b8
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5 0x2bc
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6 0x2c0
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#define QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7 0x2c4
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#define QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL 0x348
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#define QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM 0x380
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#endif
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