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c4364048ba
Add new register offsets and PHY values for SM8750. Some of the previous definitions can be leveraged from older PHY versions as offsets within registers have not changed. This also adds the required PHY sequence that is recommended after running hardware characterization. Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com> Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-4-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V8_H_
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#define QCOM_PHY_QMP_PCS_V8_H_
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/* Only for QMP V8 PHY - USB/PCIe PCS registers */
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#define QPHY_V8_PCS_SW_RESET 0x000
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#define QPHY_V8_PCS_PCS_STATUS1 0x014
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#define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
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#define QPHY_V8_PCS_START_CONTROL 0x044
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#define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
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#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
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#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
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#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V8_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0
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#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_V8_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_V8_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V8_PCS_EQ_CONFIG5 0x1ec
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#endif
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