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e961ec81a3
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
19 lines
609 B
C
19 lines
609 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_30_H_
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#define QCOM_PHY_QMP_PCS_V6_30_H_
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/* Only for QMP V6_30 PHY - PCIe PCS registers */
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#define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc
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#define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c
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#define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194
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#define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc
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#define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0
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#define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4
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#define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc
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#define QPHY_V6_30_PCS_EQ_CONFIG5 0x200
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#endif
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