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03aa45d6c6
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
26 lines
976 B
C
26 lines
976 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
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/* Only for QMP V5_20 PHY - PCIe PCS registers */
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#define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
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#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
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#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
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#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
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#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
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#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
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#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
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#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
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#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
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#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024
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#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028
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#endif
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