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a28f3cbfd1
Architecturally we have two filters for each regular event counter, so add generic support for the second one too. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: James Clark <james.clark@linaro.org> Reviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/b11be3f23a72bc27088b115099c8fe865b70babc.1741190362.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
225 lines
6.4 KiB
C
225 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* ARM CoreSight Architecture PMU driver.
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* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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*/
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#ifndef __ARM_CSPMU_H__
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#define __ARM_CSPMU_H__
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#include <linux/bitfield.h>
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#include <linux/cpumask.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#define to_arm_cspmu(p) (container_of(p, struct arm_cspmu, pmu))
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#define ARM_CSPMU_EXT_ATTR(_name, _func, _config) \
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(&((struct dev_ext_attribute[]){ \
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{ \
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.attr = __ATTR(_name, 0444, _func, NULL), \
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.var = (void *)_config \
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} \
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})[0].attr.attr)
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#define ARM_CSPMU_FORMAT_ATTR(_name, _config) \
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ARM_CSPMU_EXT_ATTR(_name, device_show_string, _config)
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#define ARM_CSPMU_EVENT_ATTR(_name, _config) \
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PMU_EVENT_ATTR_ID(_name, arm_cspmu_sysfs_event_show, _config)
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/* Default event id mask */
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#define ARM_CSPMU_EVENT_MASK GENMASK_ULL(63, 0)
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/* Default filter value mask */
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#define ARM_CSPMU_FILTER_MASK GENMASK_ULL(63, 0)
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/* Default event format */
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#define ARM_CSPMU_FORMAT_EVENT_ATTR \
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ARM_CSPMU_FORMAT_ATTR(event, "config:0-32")
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/* Default filter format */
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#define ARM_CSPMU_FORMAT_FILTER_ATTR \
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ARM_CSPMU_FORMAT_ATTR(filter, "config1:0-31")
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#define ARM_CSPMU_FORMAT_FILTER2_ATTR \
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ARM_CSPMU_FORMAT_ATTR(filter2, "config2:0-31")
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/*
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* This is the default event number for cycle count, if supported, since the
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* ARM Coresight PMU specification does not define a standard event code
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* for cycle count.
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*/
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#define ARM_CSPMU_EVT_CYCLES_DEFAULT (0x1ULL << 32)
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/*
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* The ARM Coresight PMU supports up to 256 event counters.
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* If the counters are larger-than 32-bits, then the PMU includes at
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* most 128 counters.
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*/
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#define ARM_CSPMU_MAX_HW_CNTRS 256
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/* The cycle counter, if implemented, is located at counter[31]. */
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#define ARM_CSPMU_CYCLE_CNTR_IDX 31
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/*
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* CoreSight PMU Arch register offsets.
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*/
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#define PMEVCNTR_LO 0x0
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#define PMEVCNTR_HI 0x4
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#define PMEVTYPER 0x400
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#define PMCCFILTR 0x47C
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#define PMEVFILT2R 0x800
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#define PMEVFILTR 0xA00
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#define PMCNTENSET 0xC00
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#define PMCNTENCLR 0xC20
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#define PMINTENSET 0xC40
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#define PMINTENCLR 0xC60
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#define PMOVSCLR 0xC80
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#define PMOVSSET 0xCC0
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#define PMIMPDEF 0xD80
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#define PMCFGR 0xE00
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#define PMCR 0xE04
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#define PMIIDR 0xE08
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/* PMCFGR register field */
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#define PMCFGR_NCG GENMASK(31, 28)
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#define PMCFGR_HDBG BIT(24)
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#define PMCFGR_TRO BIT(23)
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#define PMCFGR_SS BIT(22)
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#define PMCFGR_FZO BIT(21)
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#define PMCFGR_MSI BIT(20)
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#define PMCFGR_UEN BIT(19)
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#define PMCFGR_NA BIT(17)
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#define PMCFGR_EX BIT(16)
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#define PMCFGR_CCD BIT(15)
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#define PMCFGR_CC BIT(14)
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#define PMCFGR_SIZE GENMASK(13, 8)
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#define PMCFGR_N GENMASK(7, 0)
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/* PMCR register field */
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#define PMCR_TRO BIT(11)
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#define PMCR_HDBG BIT(10)
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#define PMCR_FZO BIT(9)
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#define PMCR_NA BIT(8)
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#define PMCR_DP BIT(5)
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#define PMCR_X BIT(4)
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#define PMCR_D BIT(3)
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#define PMCR_C BIT(2)
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#define PMCR_P BIT(1)
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#define PMCR_E BIT(0)
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/* PMIIDR register field */
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#define ARM_CSPMU_PMIIDR_IMPLEMENTER GENMASK(11, 0)
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#define ARM_CSPMU_PMIIDR_PRODUCTID GENMASK(31, 20)
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/* JEDEC-assigned JEP106 identification code */
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#define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
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#define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
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struct arm_cspmu;
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/* This tracks the events assigned to each counter in the PMU. */
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struct arm_cspmu_hw_events {
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/* The events that are active on the PMU for a given logical index. */
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struct perf_event **events;
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/*
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* Each bit indicates a logical counter is being used (or not) for an
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* event. If cycle counter is supported and there is a gap between
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* regular and cycle counter, the last logical counter is mapped to
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* cycle counter. Otherwise, logical and physical have 1-to-1 mapping.
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*/
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DECLARE_BITMAP(used_ctrs, ARM_CSPMU_MAX_HW_CNTRS);
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};
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/* Contains ops to query vendor/implementer specific attribute. */
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struct arm_cspmu_impl_ops {
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/* Get event attributes */
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struct attribute **(*get_event_attrs)(const struct arm_cspmu *cspmu);
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/* Get format attributes */
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struct attribute **(*get_format_attrs)(const struct arm_cspmu *cspmu);
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/* Get string identifier */
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const char *(*get_identifier)(const struct arm_cspmu *cspmu);
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/* Get PMU name to register to core perf */
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const char *(*get_name)(const struct arm_cspmu *cspmu);
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/* Check if the event corresponds to cycle count event */
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bool (*is_cycle_counter_event)(const struct perf_event *event);
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/* Decode event type/id from configs */
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u32 (*event_type)(const struct perf_event *event);
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/* Set event filters */
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void (*set_cc_filter)(struct arm_cspmu *cspmu,
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const struct perf_event *event);
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void (*set_ev_filter)(struct arm_cspmu *cspmu,
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const struct perf_event *event);
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/* Implementation specific event validation */
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int (*validate_event)(struct arm_cspmu *cspmu,
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struct perf_event *event);
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/* Hide/show unsupported events */
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umode_t (*event_attr_is_visible)(struct kobject *kobj,
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struct attribute *attr, int unused);
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};
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/* Vendor/implementer registration parameter. */
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struct arm_cspmu_impl_match {
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/* Backend module. */
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struct module *module;
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const char *module_name;
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/* PMIIDR value/mask. */
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u32 pmiidr_val;
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u32 pmiidr_mask;
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/* Callback to vendor backend to init arm_cspmu_impl::ops. */
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int (*impl_init_ops)(struct arm_cspmu *cspmu);
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};
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/* Vendor/implementer descriptor. */
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struct arm_cspmu_impl {
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u32 pmiidr;
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struct module *module;
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struct arm_cspmu_impl_match *match;
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struct arm_cspmu_impl_ops ops;
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void *ctx;
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};
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/* Coresight PMU descriptor. */
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struct arm_cspmu {
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struct pmu pmu;
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struct device *dev;
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const char *name;
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const char *identifier;
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void __iomem *base0;
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void __iomem *base1;
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cpumask_t associated_cpus;
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cpumask_t active_cpu;
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struct hlist_node cpuhp_node;
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int irq;
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bool has_atomic_dword;
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u32 pmcfgr;
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u32 num_logical_ctrs;
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u32 num_set_clr_reg;
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int cycle_counter_logical_idx;
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struct arm_cspmu_hw_events hw_events;
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const struct attribute_group *attr_groups[5];
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struct arm_cspmu_impl impl;
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};
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/* Default function to show event attribute in sysfs. */
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ssize_t arm_cspmu_sysfs_event_show(struct device *dev,
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struct device_attribute *attr,
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char *buf);
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/* Register vendor backend. */
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int arm_cspmu_impl_register(const struct arm_cspmu_impl_match *impl_match);
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/* Unregister vendor backend. */
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void arm_cspmu_impl_unregister(const struct arm_cspmu_impl_match *impl_match);
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#endif /* __ARM_CSPMU_H__ */
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