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66db1d3cbd
Add the ability to enable optional slot clock into the pwrctrl driver.
This is used to enable slot clock in split-clock topologies, where the PCIe
host/controller supply and PCIe slot supply are not provided by the same
clock. The PCIe host/controller clock should be described in the controller
node as the controller clock, while the slot clock should be described in
controller bridge/slot subnode.
Example DT snippet:
&pcicontroller {
clocks = <&clk_dif 0>; /* PCIe controller clock */
pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x0 0x0 0x0 0x0>;
compatible = "pciclass,0604";
device_type = "pci";
clocks = <&clk_dif 1>; /* PCIe slot clock */
vpcie3v3-supply = <®_3p3v>;
ranges;
};
};
Example clock topology:
____________ ____________
| PCIe host | | PCIe slot |
| | | |
| PCIe RX<|==================|>PCIe TX |
| PCIe TX<|==================|>PCIe RX |
| | | |
| PCIe CLK<|======.. ..======|>PCIe CLK |
'------------' || || '------------'
|| ||
____________ || ||
| 9FGV0441 | || ||
| | || ||
| CLK DIF0<|======'' ||
| CLK DIF1<|==========''
| CLK DIF2<|
| CLK DIF3<|
'------------'
Immutable commit for Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2024 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pci-pwrctrl.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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struct pci_pwrctrl_slot_data {
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struct pci_pwrctrl ctx;
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struct regulator_bulk_data *supplies;
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int num_supplies;
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};
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static void devm_pci_pwrctrl_slot_power_off(void *data)
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{
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struct pci_pwrctrl_slot_data *slot = data;
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regulator_bulk_disable(slot->num_supplies, slot->supplies);
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regulator_bulk_free(slot->num_supplies, slot->supplies);
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}
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static int pci_pwrctrl_slot_probe(struct platform_device *pdev)
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{
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struct pci_pwrctrl_slot_data *slot;
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struct device *dev = &pdev->dev;
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struct clk *clk;
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int ret;
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slot = devm_kzalloc(dev, sizeof(*slot), GFP_KERNEL);
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if (!slot)
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return -ENOMEM;
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ret = of_regulator_bulk_get_all(dev, dev_of_node(dev),
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&slot->supplies);
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if (ret < 0) {
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dev_err_probe(dev, ret, "Failed to get slot regulators\n");
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return ret;
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}
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slot->num_supplies = ret;
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ret = regulator_bulk_enable(slot->num_supplies, slot->supplies);
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if (ret < 0) {
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dev_err_probe(dev, ret, "Failed to enable slot regulators\n");
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goto err_regulator_free;
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}
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ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off,
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slot);
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if (ret)
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goto err_regulator_disable;
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clk = devm_clk_get_optional_enabled(dev, NULL);
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if (IS_ERR(clk)) {
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return dev_err_probe(dev, PTR_ERR(clk),
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"Failed to enable slot clock\n");
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}
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pci_pwrctrl_init(&slot->ctx, dev);
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ret = devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to register pwrctrl driver\n");
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return 0;
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err_regulator_disable:
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regulator_bulk_disable(slot->num_supplies, slot->supplies);
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err_regulator_free:
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regulator_bulk_free(slot->num_supplies, slot->supplies);
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return ret;
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}
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static const struct of_device_id pci_pwrctrl_slot_of_match[] = {
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{
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.compatible = "pciclass,0604",
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, pci_pwrctrl_slot_of_match);
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static struct platform_driver pci_pwrctrl_slot_driver = {
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.driver = {
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.name = "pci-pwrctrl-slot",
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.of_match_table = pci_pwrctrl_slot_of_match,
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},
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.probe = pci_pwrctrl_slot_probe,
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};
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module_platform_driver(pci_pwrctrl_slot_driver);
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MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
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MODULE_DESCRIPTION("Generic PCI Power Control driver for PCI Slots");
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MODULE_LICENSE("GPL");
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