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0daa521a1c
The layout struct of efuse should not do address alignment by compiler.
Otherwise it leads unexpected layout and size for certain arch suc as arm.
In x86-64, the results are identical before and after this patch.
Also adjust bit-field to prevent over adjacent byte to avoid warning:
rtw88/rtw8822b.h:66:1: note: offset of packed bit-field `res2` has changed in GCC 4.4
66 | } __packed;
| ^
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202412120131.qk0x6OhE-lkp@intel.com/
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20241212054203.135046-1-pkshih@realtek.com
189 lines
5.2 KiB
C
189 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW8822B_H__
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#define __RTW8822B_H__
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#include <asm/byteorder.h>
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#define RCR_VHT_ACK BIT(26)
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struct rtw8822bu_efuse {
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u8 res4[4]; /* 0xd0 */
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u8 usb_optional_function;
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u8 res5[0x1e];
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u8 res6[2];
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u8 serial[0x0b]; /* 0xf5 */
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u8 vid; /* 0x100 */
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u8 res7;
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u8 pid;
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u8 res8[4];
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u8 mac_addr[ETH_ALEN]; /* 0x107 */
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u8 res9[2];
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u8 vendor_name[0x07];
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u8 res10[2];
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u8 device_name[0x14];
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u8 res11[0xcf];
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u8 package_type; /* 0x1fb */
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u8 res12[0x4];
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} __packed;
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struct rtw8822be_efuse {
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u8 mac_addr[ETH_ALEN]; /* 0xd0 */
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u8 vender_id[2];
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u8 device_id[2];
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u8 sub_vender_id[2];
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u8 sub_device_id[2];
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u8 pmc[2];
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u8 exp_device_cap[2];
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u8 msi_cap;
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u8 ltr_cap; /* 0xe3 */
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u8 exp_link_control[2];
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u8 link_cap[4];
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u8 link_control[2];
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u8 serial_number[8];
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u8 res0:2; /* 0xf4 */
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u8 ltr_en:1;
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u8 res1:2;
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u8 obff:2;
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u8 res2_1:1;
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u8 res2_2:2;
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u8 obff_cap:2;
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u8 res3:4;
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u8 res4[3];
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u8 class_code[3];
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u8 pci_pm_L1_2_supp:1;
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u8 pci_pm_L1_1_supp:1;
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u8 aspm_pm_L1_2_supp:1;
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u8 aspm_pm_L1_1_supp:1;
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u8 L1_pm_substates_supp:1;
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u8 res5:3;
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u8 port_common_mode_restore_time;
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u8 port_t_power_on_scale:2;
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u8 res6:1;
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u8 port_t_power_on_value:5;
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u8 res7;
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} __packed;
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struct rtw8822bs_efuse {
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u8 res4[0x4a]; /* 0xd0 */
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u8 mac_addr[ETH_ALEN]; /* 0x11a */
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} __packed;
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struct rtw8822b_efuse {
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__le16 rtl_id;
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u8 res0[4];
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u8 usb_mode;
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u8 res1[0x09];
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/* power index for four RF paths */
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struct rtw_txpwr_idx txpwr_idx_table[4];
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u8 channel_plan; /* 0xb8 */
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u8 xtal_k;
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u8 thermal_meter;
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u8 iqk_lck;
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u8 pa_type; /* 0xbc */
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u8 lna_type_2g[2]; /* 0xbd */
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u8 lna_type_5g[2];
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u8 rf_board_option;
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u8 rf_feature_option;
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u8 rf_bt_setting;
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u8 eeprom_version;
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u8 eeprom_customer_id;
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u8 tx_bb_swing_setting_2g;
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u8 tx_bb_swing_setting_5g;
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u8 tx_pwr_calibrate_rate;
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u8 rf_antenna_option; /* 0xc9 */
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u8 rfe_option;
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u8 country_code[2];
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u8 res[3];
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union {
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struct rtw8822be_efuse e;
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struct rtw8822bu_efuse u;
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struct rtw8822bs_efuse s;
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};
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} __packed;
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static inline void
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_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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{
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/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
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rtw_write32_mask(rtwdev, addr, mask, data);
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rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
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}
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#define rtw_write32s_mask(rtwdev, addr, mask, data) \
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do { \
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BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
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\
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_rtw_write32s_mask(rtwdev, addr, mask, data); \
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} while (0)
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/* phy status page0 */
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#define GET_PHY_STAT_P0_PWDB(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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/* phy status page1 */
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#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
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#define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
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#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
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#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
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#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
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#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
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#define RTW8822B_EDCCA_MAX 0x7f
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#define RTW8822B_EDCCA_SRC_DEF 1
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#define REG_HTSTFWT 0x800
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#define REG_RXCCAMSK 0x814
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#define REG_L1WT 0x83c
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#define REG_L1PKWT 0x840
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#define REG_MRC 0x850
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#define REG_EDCCA_POW_MA 0x8a0
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#define BIT_MA_LEVEL GENMASK(1, 0)
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#define REG_ADC40 0x8c8
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#define REG_EDCCA_DECISION 0x8dc
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#define BIT_EDCCA_OPTION BIT(5)
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#define REG_CDDTXP 0x93c
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#define REG_TXPSEL1 0x940
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#define REG_EDCCA_SOURCE 0x944
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#define BIT_SOURCE_OPTION GENMASK(29, 28)
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#define REG_ACBB0 0x948
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#define REG_ACBBRXFIR 0x94c
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#define REG_ACGG2TBL 0x958
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#define REG_ADCINI 0xa04
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#define REG_TXSF2 0xa24
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#define REG_TXSF6 0xa28
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#define REG_RXDESC 0xa2c
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#define REG_ENTXCCK 0xa80
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#define REG_AGCTR_A 0xc08
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#define REG_TXDFIR 0xc20
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#define REG_TRSW 0xca0
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#define REG_RFESEL0 0xcb0
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#define REG_RFESEL8 0xcb4
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#define REG_RFECTL 0xcb8
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#define REG_RFEINV 0xcbc
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#define REG_AGCTR_B 0xe08
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#define REG_ANTWT 0x1904
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#define REG_IQKFAILMSK 0x1bf0
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extern const struct rtw_chip_info rtw8822b_hw_spec;
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#endif
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