mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
8ca4cdef93
rtl8192cu is checking rtl_mac.tids when deciding if it should enable aggregation. This is wrong because rtl_mac.tids is not initialised anywhere. Check rtl_sta_info.tids instead, which is initialised. Also, when enabling aggregation also enable RTS. The vendor driver does this, my router does this. It seems like the thing to do. Also also, it seems right to set the AMPDU density only when enabling aggregation. Also also also, delete the unused member rtl_mac.tids and the unused macros RTL_AGG_ON and RTL_AGG_OFF. Naturally, with working AMPDU the download/upload speeds are better. Before: 59/32 Mbps. After: 68/46 Mbps. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://msgid.link/4e936334-5f81-403f-a495-0628ebfb6903@gmail.com
397 lines
9.4 KiB
C
397 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#ifndef __RTL92CU_TRX_H__
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#define __RTL92CU_TRX_H__
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#define RTL92C_NUM_RX_URBS 8
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#define RTL92C_NUM_TX_URBS 32
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#define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */
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#define RX_DRV_INFO_SIZE_UNIT 8
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enum usb_rx_agg_mode {
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USB_RX_AGG_DISABLE,
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USB_RX_AGG_DMA,
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USB_RX_AGG_USB,
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USB_RX_AGG_DMA_USB
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};
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#define TX_SELE_HQ BIT(0) /* High Queue */
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#define TX_SELE_LQ BIT(1) /* Low Queue */
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#define TX_SELE_NQ BIT(2) /* Normal Queue */
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#define RTL_USB_TX_AGG_NUM_DESC 5
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#define RTL_USB_RX_AGG_PAGE_NUM 4
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#define RTL_USB_RX_AGG_PAGE_TIMEOUT 3
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#define RTL_USB_RX_AGG_BLOCK_NUM 5
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#define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3
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/*======================== rx status =========================================*/
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struct rx_drv_info_92c {
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/*
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* Driver info contain PHY status and other variabel size info
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* PHY Status content as below
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*/
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/* DWORD 0 */
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u8 gain_trsw[4];
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/* DWORD 1 */
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u8 pwdb_all;
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u8 cfosho[4];
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/* DWORD 2 */
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u8 cfotail[4];
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/* DWORD 3 */
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s8 rxevm[2];
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s8 rxsnr[4];
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/* DWORD 4 */
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u8 pdsnr[2];
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/* DWORD 5 */
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u8 csi_current[2];
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u8 csi_target[2];
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/* DWORD 6 */
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u8 sigevm;
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u8 max_ex_pwr;
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u8 ex_intf_flag:1;
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u8 sgi_en:1;
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u8 rxsc:2;
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u8 reserve:4;
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} __packed;
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/* macros to read various fields in RX descriptor */
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/* DWORD 0 */
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static inline u32 get_rx_desc_pkt_len(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, GENMASK(13, 0));
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}
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static inline u32 get_rx_desc_crc32(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, BIT(14));
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}
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static inline u32 get_rx_desc_icv(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, BIT(15));
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}
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static inline u32 get_rx_desc_drvinfo_size(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, GENMASK(19, 16));
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}
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static inline u32 get_rx_desc_shift(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, GENMASK(25, 24));
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}
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static inline u32 get_rx_desc_phy_status(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, BIT(26));
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}
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static inline u32 get_rx_desc_swdec(__le32 *__rxdesc)
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{
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return le32_get_bits(*__rxdesc, BIT(27));
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}
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/* DWORD 1 */
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static inline u32 get_rx_desc_paggr(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 1), BIT(14));
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}
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static inline u32 get_rx_desc_faggr(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 1), BIT(15));
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}
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/* DWORD 3 */
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static inline u32 get_rx_desc_rx_mcs(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 3), GENMASK(5, 0));
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}
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static inline u32 get_rx_desc_rx_ht(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 3), BIT(6));
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}
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static inline u32 get_rx_desc_splcp(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 3), BIT(8));
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}
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static inline u32 get_rx_desc_bw(__le32 *__rxdesc)
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{
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return le32_get_bits(*(__rxdesc + 3), BIT(9));
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}
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/* DWORD 5 */
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static inline u32 get_rx_desc_tsfl(__le32 *__rxdesc)
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{
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return le32_to_cpu(*((__rxdesc + 5)));
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}
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/*======================= tx desc ============================================*/
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/* macros to set various fields in TX descriptor */
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/* Dword 0 */
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static inline void set_tx_desc_pkt_size(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, GENMASK(15, 0));
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}
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static inline void set_tx_desc_offset(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, GENMASK(23, 16));
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}
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static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(24));
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}
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static inline void set_tx_desc_htc(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(25));
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}
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static inline void set_tx_desc_last_seg(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(26));
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}
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static inline void set_tx_desc_first_seg(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(27));
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}
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static inline void set_tx_desc_linip(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(28));
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}
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static inline void set_tx_desc_own(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits(__txdesc, __value, BIT(31));
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}
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/* Dword 1 */
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static inline void set_tx_desc_macid(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, GENMASK(4, 0));
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}
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static inline void set_tx_desc_agg_enable(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, BIT(5));
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}
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static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, BIT(6));
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}
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static inline void set_tx_desc_rdg_enable(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, BIT(7));
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}
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static inline void set_tx_desc_queue_sel(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, GENMASK(12, 8));
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}
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static inline void set_tx_desc_rate_id(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, GENMASK(19, 16));
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}
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static inline void set_tx_desc_nav_use_hdr(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, BIT(20));
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}
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static inline void set_tx_desc_sec_type(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, GENMASK(23, 22));
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}
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static inline void set_tx_desc_pkt_offset(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 1), __value, GENMASK(30, 26));
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}
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/* Dword 2 */
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static inline void set_tx_desc_more_frag(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 2), __value, BIT(17));
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}
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static inline void set_tx_desc_ampdu_density(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 2), __value, GENMASK(22, 20));
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}
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/* Dword 3 */
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static inline void set_tx_desc_seq(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 3), __value, GENMASK(27, 16));
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}
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static inline void set_tx_desc_pkt_id(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 3), __value, GENMASK(31, 28));
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}
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/* Dword 4 */
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static inline void set_tx_desc_rts_rate(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, GENMASK(4, 0));
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}
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static inline void set_tx_desc_qos(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(6));
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}
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static inline void set_tx_desc_hwseq_en(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(7));
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}
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static inline void set_tx_desc_use_rate(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(8));
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}
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static inline void set_tx_desc_disable_fb(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(10));
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}
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static inline void set_tx_desc_cts2self(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(11));
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}
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static inline void set_tx_desc_rts_enable(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(12));
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}
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static inline void set_tx_desc_hw_rts_enable(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(13));
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}
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static inline void set_tx_desc_data_sc(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, GENMASK(21, 20));
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}
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static inline void set_tx_desc_data_bw(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(25));
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}
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static inline void set_tx_desc_rts_short(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(26));
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}
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static inline void set_tx_desc_rts_bw(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, BIT(27));
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}
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static inline void set_tx_desc_rts_sc(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, GENMASK(29, 28));
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}
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static inline void set_tx_desc_rts_stbc(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 4), __value, GENMASK(31, 30));
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}
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/* Dword 5 */
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static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
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}
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static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val)
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{
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le32p_replace_bits((__pdesc + 5), __val, BIT(6));
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}
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static inline void set_tx_desc_data_rate_fb_limit(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 5), __value, GENMASK(12, 8));
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}
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static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 5), __value, GENMASK(16, 13));
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}
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/* Dword 6 */
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static inline void set_tx_desc_max_agg_num(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 6), __value, GENMASK(15, 11));
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}
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/* Dword 7 */
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static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value)
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{
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le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0));
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}
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int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw);
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u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index);
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bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
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struct rtl_stats *stats,
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struct ieee80211_rx_status *rx_status,
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u8 *p_desc, struct sk_buff *skb);
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void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb);
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void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb);
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int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
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struct sk_buff *skb);
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struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *,
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struct sk_buff_head *);
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void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
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struct ieee80211_hdr *hdr, u8 *pdesc_tx,
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u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
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struct ieee80211_sta *sta,
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struct sk_buff *skb,
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u8 queue_index,
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struct rtl_tcb_desc *tcb_desc);
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void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
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struct sk_buff *skb);
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#endif
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