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46d55fcec1
Send EAPOL frames via control path so they can be treated in a different way rather than normal data frames. In this case EAPOLs are sent with higher priority and with disabled aggregation and encryption. Besides, all devices benefit from sending EAPOL frames via high priority path, so move the functionality from chip specific to common code. Signed-off-by: Igor Mitsyanko <igor.mitsyanko.os@quantenna.com> Signed-off-by: Sergey Matyukevich <sergey.matyukevich.os@quantenna.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2018 Quantenna Communications, Inc. All rights reserved. */
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#ifndef _QTN_FMAC_PCIE_H_
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#define _QTN_FMAC_PCIE_H_
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/skbuff.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include "shm_ipc.h"
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#include "bus.h"
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#define SKB_BUF_SIZE 2048
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#define QTN_FW_DL_TIMEOUT_MS 3000
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#define QTN_FW_QLINK_TIMEOUT_MS 30000
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#define QTN_EP_RESET_WAIT_MS 1000
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struct qtnf_pcie_bus_priv {
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struct pci_dev *pdev;
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int (*probe_cb)(struct qtnf_bus *bus, unsigned int tx_bd_size,
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unsigned int rx_bd_size);
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void (*remove_cb)(struct qtnf_bus *bus);
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int (*suspend_cb)(struct qtnf_bus *bus);
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int (*resume_cb)(struct qtnf_bus *bus);
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u64 (*dma_mask_get_cb)(void);
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spinlock_t tx_reclaim_lock;
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spinlock_t tx_lock;
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struct workqueue_struct *workqueue;
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struct tasklet_struct reclaim_tq;
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void __iomem *sysctl_bar;
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void __iomem *epmem_bar;
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void __iomem *dmareg_bar;
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struct qtnf_shm_ipc shm_ipc_ep_in;
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struct qtnf_shm_ipc shm_ipc_ep_out;
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u16 tx_bd_num;
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u16 rx_bd_num;
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struct sk_buff **tx_skb;
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struct sk_buff **rx_skb;
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unsigned int fw_blksize;
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u32 rx_bd_w_index;
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u32 rx_bd_r_index;
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u32 tx_bd_w_index;
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u32 tx_bd_r_index;
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/* diagnostics stats */
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u32 pcie_irq_count;
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u32 tx_full_count;
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u32 tx_done_count;
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u32 tx_reclaim_done;
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u32 tx_reclaim_req;
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u8 msi_enabled;
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u8 tx_stopped;
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bool flashboot;
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};
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int qtnf_pcie_control_tx(struct qtnf_bus *bus, struct sk_buff *skb);
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int qtnf_pcie_alloc_skb_array(struct qtnf_pcie_bus_priv *priv);
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int qtnf_pcie_fw_boot_done(struct qtnf_bus *bus);
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void qtnf_pcie_init_shm_ipc(struct qtnf_pcie_bus_priv *priv,
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struct qtnf_shm_ipc_region __iomem *ipc_tx_reg,
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struct qtnf_shm_ipc_region __iomem *ipc_rx_reg,
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const struct qtnf_shm_ipc_int *ipc_int);
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struct qtnf_bus *qtnf_pcie_pearl_alloc(struct pci_dev *pdev);
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struct qtnf_bus *qtnf_pcie_topaz_alloc(struct pci_dev *pdev);
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static inline void qtnf_non_posted_write(u32 val, void __iomem *basereg)
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{
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writel(val, basereg);
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/* flush posted write */
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readl(basereg);
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}
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#endif /* _QTN_FMAC_PCIE_H_ */
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