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WCN7850 uses error dst ring as mon dest ring. Each time hardware receives a packet, will fill the payload into mon dest ring. The mon dest ring may store many MSDUs, which belonged to different MPDUs. Need to retrieve MSDUs based on the PPDU ID, only processing the MSDUs with same PPDU ID each time. The PPDU ID is used in cycles, the difference between the PPDU IDs of the two rings must be checked. If the status PPDU ID minus the dest PPDU ID is greater than 20000, it is considered a wrap-around case. After reaping the mon dest ring, should prepare packet and deliver it to mac80211 when status PPDU ID is equal to dest PPDU ID. Then start to process next PPDU if exists. But if dest PPDU ID > status PPDU ID, should hold on to mon dest ring processing. If it exceeds 16 consecutive times, status PPDU ID will be forcibly set to dest PPDU ID to avoid backpressure issue. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.3.1-00173-QCAHKSWPL_SILICONZ-1 Signed-off-by: Kang Yang <kang.yang@oss.qualcomm.com> Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com> Link: https://patch.msgid.link/20250421023444.1778-11-kang.yang@oss.qualcomm.com Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
1169 lines
36 KiB
C
1169 lines
36 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
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/*
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* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef ATH12K_HAL_RX_H
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#define ATH12K_HAL_RX_H
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struct hal_rx_wbm_rel_info {
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u32 cookie;
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enum hal_wbm_rel_src_module err_rel_src;
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enum hal_reo_dest_ring_push_reason push_reason;
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u32 err_code;
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bool first_msdu;
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bool last_msdu;
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bool continuation;
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void *rx_desc;
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bool hw_cc_done;
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};
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#define HAL_INVALID_PEERID 0x3fff
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#define VHT_SIG_SU_NSS_MASK 0x7
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#define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
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le32_get_bits((__val), GENMASK(7, 0))
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#define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
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le32_get_bits((__val), GENMASK(15, 8))
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#define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
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le32_get_bits((__val), GENMASK(23, 16))
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#define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
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le32_get_bits((__val), GENMASK(31, 24))
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struct hal_rx_mon_status_tlv_hdr {
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u32 hdr;
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u8 value[];
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};
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enum hal_rx_su_mu_coding {
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HAL_RX_SU_MU_CODING_BCC,
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HAL_RX_SU_MU_CODING_LDPC,
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HAL_RX_SU_MU_CODING_MAX,
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};
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enum hal_rx_gi {
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HAL_RX_GI_0_8_US,
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HAL_RX_GI_0_4_US,
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HAL_RX_GI_1_6_US,
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HAL_RX_GI_3_2_US,
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HAL_RX_GI_MAX,
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};
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enum hal_rx_bw {
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HAL_RX_BW_20MHZ,
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HAL_RX_BW_40MHZ,
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HAL_RX_BW_80MHZ,
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HAL_RX_BW_160MHZ,
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HAL_RX_BW_320MHZ,
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HAL_RX_BW_MAX,
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};
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enum hal_rx_preamble {
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HAL_RX_PREAMBLE_11A,
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HAL_RX_PREAMBLE_11B,
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HAL_RX_PREAMBLE_11N,
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HAL_RX_PREAMBLE_11AC,
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HAL_RX_PREAMBLE_11AX,
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HAL_RX_PREAMBLE_11BA,
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HAL_RX_PREAMBLE_11BE,
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HAL_RX_PREAMBLE_MAX,
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};
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enum hal_rx_reception_type {
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HAL_RX_RECEPTION_TYPE_SU,
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HAL_RX_RECEPTION_TYPE_MU_MIMO,
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HAL_RX_RECEPTION_TYPE_MU_OFDMA,
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HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
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HAL_RX_RECEPTION_TYPE_MAX,
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};
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enum hal_rx_legacy_rate {
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HAL_RX_LEGACY_RATE_1_MBPS,
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HAL_RX_LEGACY_RATE_2_MBPS,
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HAL_RX_LEGACY_RATE_5_5_MBPS,
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HAL_RX_LEGACY_RATE_6_MBPS,
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HAL_RX_LEGACY_RATE_9_MBPS,
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HAL_RX_LEGACY_RATE_11_MBPS,
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HAL_RX_LEGACY_RATE_12_MBPS,
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HAL_RX_LEGACY_RATE_18_MBPS,
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HAL_RX_LEGACY_RATE_24_MBPS,
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HAL_RX_LEGACY_RATE_36_MBPS,
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HAL_RX_LEGACY_RATE_48_MBPS,
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HAL_RX_LEGACY_RATE_54_MBPS,
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HAL_RX_LEGACY_RATE_INVALID,
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};
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#define HAL_TLV_STATUS_PPDU_NOT_DONE 0
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#define HAL_TLV_STATUS_PPDU_DONE 1
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#define HAL_TLV_STATUS_BUF_DONE 2
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#define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
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#define HAL_RX_FCS_LEN 4
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enum hal_rx_mon_status {
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HAL_RX_MON_STATUS_PPDU_NOT_DONE,
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HAL_RX_MON_STATUS_PPDU_DONE,
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HAL_RX_MON_STATUS_BUF_DONE,
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HAL_RX_MON_STATUS_BUF_ADDR,
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HAL_RX_MON_STATUS_MPDU_START,
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HAL_RX_MON_STATUS_MPDU_END,
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HAL_RX_MON_STATUS_MSDU_END,
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};
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#define HAL_RX_MAX_MPDU 1024
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#define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
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struct hal_rx_user_status {
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u32 mcs:4,
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nss:3,
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ofdma_info_valid:1,
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ul_ofdma_ru_start_index:7,
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ul_ofdma_ru_width:7,
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ul_ofdma_ru_size:8;
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u32 ul_ofdma_user_v0_word0;
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u32 ul_ofdma_user_v0_word1;
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u32 ast_index;
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u32 tid;
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u16 tcp_msdu_count;
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u16 tcp_ack_msdu_count;
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u16 udp_msdu_count;
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u16 other_msdu_count;
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u16 frame_control;
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u8 frame_control_info_valid;
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u8 data_sequence_control_info_valid;
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u16 first_data_seq_ctrl;
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u32 preamble_type;
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u16 ht_flags;
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u16 vht_flags;
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u16 he_flags;
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u8 rs_flags;
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u8 ldpc;
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u32 mpdu_cnt_fcs_ok;
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u32 mpdu_cnt_fcs_err;
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u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
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u32 mpdu_ok_byte_count;
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u32 mpdu_err_byte_count;
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bool ampdu_present;
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u16 ampdu_id;
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};
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#define HAL_MAX_UL_MU_USERS 37
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struct hal_rx_u_sig_info {
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bool ul_dl;
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u8 bw;
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u8 ppdu_type_comp_mode;
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u8 eht_sig_mcs;
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u8 num_eht_sig_sym;
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struct ieee80211_radiotap_eht_usig usig;
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};
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#define HAL_RX_MON_MAX_AGGR_SIZE 128
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struct hal_rx_tlv_aggr_info {
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bool in_progress;
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u16 cur_len;
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u16 tlv_tag;
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u8 buf[HAL_RX_MON_MAX_AGGR_SIZE];
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};
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struct hal_rx_radiotap_eht {
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__le32 known;
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__le32 data[9];
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};
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#define EHT_MAX_USER_INFO 4
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struct hal_rx_eht_info {
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u8 num_user_info;
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struct hal_rx_radiotap_eht eht;
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u32 user_info[EHT_MAX_USER_INFO];
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};
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struct hal_rx_mon_ppdu_info {
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u32 ppdu_id;
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u32 last_ppdu_id;
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u64 ppdu_ts;
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u32 num_mpdu_fcs_ok;
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u32 num_mpdu_fcs_err;
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u32 preamble_type;
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u32 mpdu_len;
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u16 chan_num;
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u16 freq;
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u16 tcp_msdu_count;
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u16 tcp_ack_msdu_count;
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u16 udp_msdu_count;
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u16 other_msdu_count;
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u16 peer_id;
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u8 rate;
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u8 mcs;
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u8 nss;
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u8 bw;
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u8 vht_flag_values1;
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u8 vht_flag_values2;
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u8 vht_flag_values3[4];
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u8 vht_flag_values4;
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u8 vht_flag_values5;
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u16 vht_flag_values6;
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u8 is_stbc;
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u8 gi;
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u8 sgi;
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u8 ldpc;
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u8 beamformed;
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u8 rssi_comb;
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u16 tid;
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u8 fc_valid;
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u16 ht_flags;
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u16 vht_flags;
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u16 he_flags;
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u16 he_mu_flags;
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u8 dcm;
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u8 ru_alloc;
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u8 reception_type;
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u64 tsft;
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u64 rx_duration;
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u16 frame_control;
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u32 ast_index;
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u8 rs_fcs_err;
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u8 rs_flags;
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u8 cck_flag;
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u8 ofdm_flag;
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u8 ulofdma_flag;
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u8 frame_control_info_valid;
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u16 he_per_user_1;
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u16 he_per_user_2;
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u8 he_per_user_position;
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u8 he_per_user_known;
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u16 he_flags1;
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u16 he_flags2;
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u8 he_RU[4];
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u16 he_data1;
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u16 he_data2;
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u16 he_data3;
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u16 he_data4;
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u16 he_data5;
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u16 he_data6;
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u32 ppdu_len;
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u32 prev_ppdu_id;
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u32 device_id;
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u16 first_data_seq_ctrl;
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u8 monitor_direct_used;
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u8 data_sequence_control_info_valid;
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u8 ltf_size;
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u8 rxpcu_filter_pass;
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s8 rssi_chain[8][8];
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u32 num_users;
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u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
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u8 addr1[ETH_ALEN];
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u8 addr2[ETH_ALEN];
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u8 addr3[ETH_ALEN];
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u8 addr4[ETH_ALEN];
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struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
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u8 userid;
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bool first_msdu_in_mpdu;
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bool is_ampdu;
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u8 medium_prot_type;
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bool ppdu_continuation;
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bool eht_usig;
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struct hal_rx_u_sig_info u_sig_info;
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bool is_eht;
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struct hal_rx_eht_info eht_info;
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struct hal_rx_tlv_aggr_info tlv_aggr;
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};
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#define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
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#define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0)
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#define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16)
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struct hal_rx_ppdu_start {
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__le32 info0;
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__le32 info1;
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__le32 ppdu_start_ts_31_0;
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__le32 ppdu_start_ts_63_32;
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__le32 rsvd[2];
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} __packed;
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#define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID GENMASK(15, 14)
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#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11)
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#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12)
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#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13)
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#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21)
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#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
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#define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
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#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
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struct hal_rx_ppdu_end_user_stats {
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__le32 rsvd0[2];
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__le32 info0;
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__le32 info1;
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__le32 info2;
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__le32 info3;
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__le32 ht_ctrl;
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__le32 rsvd1[2];
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__le32 info4;
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__le32 info5;
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__le32 usr_resp_ref;
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__le32 info6;
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__le32 rsvd3[4];
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__le32 info7;
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__le32 rsvd4;
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__le32 info8;
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__le32 rsvd5[2];
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__le32 usr_resp_ref_ext;
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__le32 rsvd6;
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} __packed;
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struct hal_rx_ppdu_end_user_stats_ext {
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__le32 info0;
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__le32 info1;
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__le32 info2;
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__le32 info3;
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__le32 info4;
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__le32 info5;
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__le32 info6;
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__le32 rsvd;
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} __packed;
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#define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
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#define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
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#define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
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#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
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#define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
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struct hal_rx_ht_sig_info {
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__le32 info0;
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__le32 info1;
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} __packed;
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#define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
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#define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
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struct hal_rx_lsig_b_info {
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__le32 info0;
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} __packed;
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#define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
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#define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
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#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
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struct hal_rx_lsig_a_info {
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__le32 info0;
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} __packed;
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#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
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#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
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#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
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#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
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#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
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#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
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#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
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#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
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struct hal_rx_vht_sig_a_info {
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__le32 info0;
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__le32 info1;
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} __packed;
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enum hal_rx_vht_sig_a_gi_setting {
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HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
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HAL_RX_VHT_SIG_A_SHORT_GI = 1,
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HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
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};
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#define HE_GI_0_8 0
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#define HE_GI_0_4 1
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#define HE_GI_1_6 2
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#define HE_GI_3_2 3
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#define HE_LTF_1_X 0
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#define HE_LTF_2_X 1
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#define HE_LTF_4_X 2
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
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#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
|
|
#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
|
|
|
|
struct hal_rx_he_sig_a_su_info {
|
|
__le32 info0;
|
|
__le32 info1;
|
|
} __packed;
|
|
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG BIT(1)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB GENMASK(3, 1)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB BIT(4)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR GENMASK(10, 5)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE GENMASK(14, 11)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW GENMASK(17, 15)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB BIT(22)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE GENMASK(24, 23)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25)
|
|
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
|
|
#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15)
|
|
|
|
struct hal_rx_he_sig_a_mu_dl_info {
|
|
__le32 info0;
|
|
__le32 info1;
|
|
} __packed;
|
|
|
|
#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
|
|
|
|
struct hal_rx_he_sig_b1_mu_info {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
|
|
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
|
|
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
|
|
#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
|
|
|
|
struct hal_rx_he_sig_b2_mu_info {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14)
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
|
|
#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
|
|
|
|
struct hal_rx_he_sig_b2_ofdma_info {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
enum hal_rx_ul_reception_type {
|
|
HAL_RECEPTION_TYPE_ULOFMDA,
|
|
HAL_RECEPTION_TYPE_ULMIMO,
|
|
HAL_RECEPTION_TYPE_OTHER,
|
|
HAL_RECEPTION_TYPE_FRAMELESS
|
|
};
|
|
|
|
#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0)
|
|
#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5)
|
|
#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
|
|
|
|
struct hal_rx_phyrx_rssi_legacy_info {
|
|
__le32 info0;
|
|
__le32 rsvd0[39];
|
|
__le32 info1;
|
|
__le32 rsvd1;
|
|
} __packed;
|
|
|
|
#define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16)
|
|
#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16)
|
|
#define HAL_RX_MPDU_START_INFO1_DEVICE_ID GENMASK(31, 30)
|
|
#define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0)
|
|
struct hal_rx_mpdu_start {
|
|
__le32 rsvd0[9];
|
|
__le32 info0;
|
|
__le32 info1;
|
|
__le32 rsvd1[2];
|
|
__le32 info2;
|
|
__le32 rsvd2[16];
|
|
} __packed;
|
|
|
|
struct hal_rx_msdu_end {
|
|
__le32 info0;
|
|
__le32 rsvd0[9];
|
|
__le16 info00;
|
|
__le16 info01;
|
|
__le32 rsvd00[8];
|
|
__le32 info1;
|
|
__le32 rsvd1[10];
|
|
__le32 info2;
|
|
__le32 rsvd2;
|
|
} __packed;
|
|
|
|
#define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
|
|
struct hal_rx_ppdu_end_duration {
|
|
__le32 rsvd0[9];
|
|
__le32 info0;
|
|
__le32 rsvd1[18];
|
|
} __packed;
|
|
|
|
struct hal_rx_rxpcu_classification_overview {
|
|
u32 rsvd0;
|
|
} __packed;
|
|
|
|
struct hal_rx_msdu_desc_info {
|
|
u32 msdu_flags;
|
|
u16 msdu_len; /* 14 bits for length */
|
|
};
|
|
|
|
#define HAL_RX_NUM_MSDU_DESC 6
|
|
struct hal_rx_msdu_list {
|
|
struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
|
|
u64 paddr[HAL_RX_NUM_MSDU_DESC];
|
|
u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
|
|
u8 rbm[HAL_RX_NUM_MSDU_DESC];
|
|
};
|
|
|
|
#define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0 GENMASK(31, 0)
|
|
#define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32 GENMASK(15, 0)
|
|
#define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0 GENMASK(31, 16)
|
|
#define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16 GENMASK(31, 0)
|
|
|
|
struct hal_rx_frame_bitmap_ack {
|
|
__le32 reserved;
|
|
__le32 info0;
|
|
__le32 info1;
|
|
__le32 info2;
|
|
__le32 reserved1[10];
|
|
} __packed;
|
|
|
|
#define HAL_RX_RESP_REQ_INFO0_PPDU_ID GENMASK(15, 0)
|
|
#define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE BIT(16)
|
|
#define HAL_RX_RESP_REQ_INFO1_DURATION GENMASK(15, 0)
|
|
#define HAL_RX_RESP_REQ_INFO1_RATE_MCS GENMASK(24, 21)
|
|
#define HAL_RX_RESP_REQ_INFO1_SGI GENMASK(26, 25)
|
|
#define HAL_RX_RESP_REQ_INFO1_STBC BIT(27)
|
|
#define HAL_RX_RESP_REQ_INFO1_LDPC BIT(28)
|
|
#define HAL_RX_RESP_REQ_INFO1_IS_AMPDU BIT(29)
|
|
#define HAL_RX_RESP_REQ_INFO2_NUM_USER GENMASK(6, 0)
|
|
#define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0 GENMASK(31, 0)
|
|
#define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32 GENMASK(15, 0)
|
|
#define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0 GENMASK(31, 16)
|
|
#define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16 GENMASK(31, 0)
|
|
|
|
struct hal_rx_resp_req_info {
|
|
__le32 info0;
|
|
__le32 reserved[1];
|
|
__le32 info1;
|
|
__le32 info2;
|
|
__le32 reserved1[2];
|
|
__le32 info3;
|
|
__le32 info4;
|
|
__le32 info5;
|
|
__le32 reserved2[5];
|
|
} __packed;
|
|
|
|
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
|
|
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
|
|
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
|
|
#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
|
|
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID BIT(30)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER BIT(31)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS GENMASK(2, 0)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS GENMASK(6, 3)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC BIT(7)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM BIT(8)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START GENMASK(15, 9)
|
|
#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE GENMASK(18, 16)
|
|
|
|
/* HE Radiotap data1 Mask */
|
|
#define HE_SU_FORMAT_TYPE 0x0000
|
|
#define HE_EXT_SU_FORMAT_TYPE 0x0001
|
|
#define HE_MU_FORMAT_TYPE 0x0002
|
|
#define HE_TRIG_FORMAT_TYPE 0x0003
|
|
#define HE_BEAM_CHANGE_KNOWN 0x0008
|
|
#define HE_DL_UL_KNOWN 0x0010
|
|
#define HE_MCS_KNOWN 0x0020
|
|
#define HE_DCM_KNOWN 0x0040
|
|
#define HE_CODING_KNOWN 0x0080
|
|
#define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
|
|
#define HE_STBC_KNOWN 0x0200
|
|
#define HE_DATA_BW_RU_KNOWN 0x4000
|
|
#define HE_DOPPLER_KNOWN 0x8000
|
|
#define HE_BSS_COLOR_KNOWN 0x0004
|
|
|
|
/* HE Radiotap data2 Mask */
|
|
#define HE_GI_KNOWN 0x0002
|
|
#define HE_TXBF_KNOWN 0x0010
|
|
#define HE_PE_DISAMBIGUITY_KNOWN 0x0020
|
|
#define HE_TXOP_KNOWN 0x0040
|
|
#define HE_LTF_SYMBOLS_KNOWN 0x0004
|
|
#define HE_PRE_FEC_PADDING_KNOWN 0x0008
|
|
#define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
|
|
|
|
/* HE radiotap data3 shift values */
|
|
#define HE_BEAM_CHANGE_SHIFT 6
|
|
#define HE_DL_UL_SHIFT 7
|
|
#define HE_TRANSMIT_MCS_SHIFT 8
|
|
#define HE_DCM_SHIFT 12
|
|
#define HE_CODING_SHIFT 13
|
|
#define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
|
|
#define HE_STBC_SHIFT 15
|
|
|
|
/* HE radiotap data4 shift values */
|
|
#define HE_STA_ID_SHIFT 4
|
|
|
|
/* HE radiotap data5 */
|
|
#define HE_GI_SHIFT 4
|
|
#define HE_LTF_SIZE_SHIFT 6
|
|
#define HE_LTF_SYM_SHIFT 8
|
|
#define HE_TXBF_SHIFT 14
|
|
#define HE_PE_DISAMBIGUITY_SHIFT 15
|
|
#define HE_PRE_FEC_PAD_SHIFT 12
|
|
|
|
/* HE radiotap data6 */
|
|
#define HE_DOPPLER_SHIFT 4
|
|
#define HE_TXOP_SHIFT 8
|
|
|
|
/* HE radiotap HE-MU flags1 */
|
|
#define HE_SIG_B_MCS_KNOWN 0x0010
|
|
#define HE_SIG_B_DCM_KNOWN 0x0040
|
|
#define HE_SIG_B_SYM_NUM_KNOWN 0x8000
|
|
#define HE_RU_0_KNOWN 0x0100
|
|
#define HE_RU_1_KNOWN 0x0200
|
|
#define HE_RU_2_KNOWN 0x0400
|
|
#define HE_RU_3_KNOWN 0x0800
|
|
#define HE_DCM_FLAG_1_SHIFT 5
|
|
#define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
|
|
#define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
|
|
|
|
/* HE radiotap HE-MU flags2 */
|
|
#define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
|
|
#define HE_BW_KNOWN 0x0004
|
|
#define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
|
|
#define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
|
|
#define HE_NUM_SIG_B_FLAG_2_SHIFT 9
|
|
#define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
|
|
#define HE_LTF_KNOWN 0x8000
|
|
|
|
/* HE radiotap per_user_1 */
|
|
#define HE_STA_SPATIAL_SHIFT 11
|
|
#define HE_TXBF_SHIFT 14
|
|
#define HE_RESERVED_SET_TO_1_SHIFT 19
|
|
#define HE_STA_CODING_SHIFT 20
|
|
|
|
/* HE radiotap per_user_2 */
|
|
#define HE_STA_MCS_SHIFT 4
|
|
#define HE_STA_DCM_SHIFT 5
|
|
|
|
/* HE radiotap per user known */
|
|
#define HE_USER_FIELD_POSITION_KNOWN 0x01
|
|
#define HE_STA_ID_PER_USER_KNOWN 0x02
|
|
#define HE_STA_NSTS_KNOWN 0x04
|
|
#define HE_STA_TX_BF_KNOWN 0x08
|
|
#define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
|
|
#define HE_STA_MCS_KNOWN 0x20
|
|
#define HE_STA_DCM_KNOWN 0x40
|
|
#define HE_STA_CODING_KNOWN 0x80
|
|
|
|
#define HAL_RX_MPDU_ERR_FCS BIT(0)
|
|
#define HAL_RX_MPDU_ERR_DECRYPT BIT(1)
|
|
#define HAL_RX_MPDU_ERR_TKIP_MIC BIT(2)
|
|
#define HAL_RX_MPDU_ERR_AMSDU_ERR BIT(3)
|
|
#define HAL_RX_MPDU_ERR_OVERFLOW BIT(4)
|
|
#define HAL_RX_MPDU_ERR_MSDU_LEN BIT(5)
|
|
#define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6)
|
|
#define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7)
|
|
|
|
#define HAL_RX_PHY_CMN_USER_INFO0_GI GENMASK(17, 16)
|
|
|
|
struct hal_phyrx_common_user_info {
|
|
__le32 rsvd[2];
|
|
__le32 info0;
|
|
__le32 rsvd1;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE GENMASK(3, 0)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF GENMASK(5, 4)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM GENMASK(8, 6)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS GENMASK(10, 7)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED BIT(11)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD GENMASK(13, 12)
|
|
#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC GENMASK(17, 14)
|
|
|
|
struct hal_eht_sig_ndp_cmn_eb {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE GENMASK(3, 0)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF GENMASK(5, 4)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM GENMASK(8, 6)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM BIT(9)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY BIT(12)
|
|
#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD GENMASK(16, 13)
|
|
|
|
struct hal_eht_sig_usig_overflow {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_VALIDATE BIT(15)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS GENMASK(19, 16)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED BIT(20)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING BIT(21)
|
|
#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC GENMASK(25, 22)
|
|
|
|
struct hal_eht_sig_non_mu_mimo {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0)
|
|
#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS GENMASK(14, 11)
|
|
#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING BIT(15)
|
|
#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING GENMASK(22, 16)
|
|
#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC GENMASK(26, 23)
|
|
|
|
struct hal_eht_sig_mu_mimo {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
union hal_eht_sig_user_field {
|
|
struct hal_eht_sig_mu_mimo mu_mimo;
|
|
struct hal_eht_sig_non_mu_mimo n_mu_mimo;
|
|
};
|
|
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE GENMASK(3, 0)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF GENMASK(5, 4)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM GENMASK(8, 6)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_LDPC_EXTA_SYM BIT(9)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISAMBIGUITY BIT(12)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD GENMASK(16, 13)
|
|
#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS GENMASK(19, 17)
|
|
|
|
struct hal_eht_sig_non_ofdma_cmn_eb {
|
|
__le32 info0;
|
|
union hal_eht_sig_user_field user_field;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE GENMASK_ULL(3, 0)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF GENMASK_ULL(5, 4)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM GENMASK_ULL(8, 6)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_LDPC_EXTRA_SYM BIT(9)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR GENMASK_ULL(11, 10)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_DISAMBIGUITY BIT(12)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD GENMASK_ULL(16, 13)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1 GENMASK_ULL(25, 17)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2 GENMASK_ULL(34, 26)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB1_CRC GENMASK_ULL(30, 27)
|
|
|
|
struct hal_eht_sig_ofdma_cmn_eb1 {
|
|
__le64 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1 GENMASK_ULL(8, 0)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2 GENMASK_ULL(17, 9)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3 GENMASK_ULL(26, 18)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4 GENMASK_ULL(35, 27)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5 GENMASK_ULL(44, 36)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6 GENMASK_ULL(53, 45)
|
|
#define HAL_RX_EHT_SIG_OFDMA_EB2_MCS GNEMASK_ULL(57, 54)
|
|
|
|
struct hal_eht_sig_ofdma_cmn_eb2 {
|
|
__le64 info0;
|
|
} __packed;
|
|
|
|
struct hal_eht_sig_ofdma_cmn_eb {
|
|
struct hal_eht_sig_ofdma_cmn_eb1 eb1;
|
|
struct hal_eht_sig_ofdma_cmn_eb2 eb2;
|
|
union hal_eht_sig_user_field user_field;
|
|
} __packed;
|
|
|
|
enum hal_eht_bw {
|
|
HAL_EHT_BW_20,
|
|
HAL_EHT_BW_40,
|
|
HAL_EHT_BW_80,
|
|
HAL_EHT_BW_160,
|
|
HAL_EHT_BW_320_1,
|
|
HAL_EHT_BW_320_2,
|
|
};
|
|
|
|
#define HAL_RX_USIG_CMN_INFO0_PHY_VERSION GENMASK(2, 0)
|
|
#define HAL_RX_USIG_CMN_INFO0_BW GENMASK(5, 3)
|
|
#define HAL_RX_USIG_CMN_INFO0_UL_DL BIT(6)
|
|
#define HAL_RX_USIG_CMN_INFO0_BSS_COLOR GENMASK(12, 7)
|
|
#define HAL_RX_USIG_CMN_INFO0_TXOP GENMASK(19, 13)
|
|
#define HAL_RX_USIG_CMN_INFO0_DISREGARD GENMASK(25, 20)
|
|
#define HAL_RX_USIG_CMN_INFO0_VALIDATE BIT(26)
|
|
|
|
struct hal_mon_usig_cmn {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
|
|
#define HAL_RX_USIG_TB_INFO0_VALIDATE BIT(2)
|
|
#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1 GENMASK(6, 3)
|
|
#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2 GENMASK(10, 7)
|
|
#define HAL_RX_USIG_TB_INFO0_DISREGARD_1 GENMASK(15, 11)
|
|
#define HAL_RX_USIG_TB_INFO0_CRC GENMASK(19, 16)
|
|
#define HAL_RX_USIG_TB_INFO0_TAIL GENMASK(25, 20)
|
|
#define HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS BIT(31)
|
|
|
|
struct hal_mon_usig_tb {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
#define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0)
|
|
#define HAL_RX_USIG_MU_INFO0_VALIDATE_1 BIT(2)
|
|
#define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO GENMASK(7, 3)
|
|
#define HAL_RX_USIG_MU_INFO0_VALIDATE_2 BIT(8)
|
|
#define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS GENMASK(10, 9)
|
|
#define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM GENMASK(15, 11)
|
|
#define HAL_RX_USIG_MU_INFO0_CRC GENMASK(20, 16)
|
|
#define HAL_RX_USIG_MU_INFO0_TAIL GENMASK(26, 21)
|
|
#define HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS BIT(31)
|
|
|
|
struct hal_mon_usig_mu {
|
|
__le32 info0;
|
|
} __packed;
|
|
|
|
union hal_mon_usig_non_cmn {
|
|
struct hal_mon_usig_tb tb;
|
|
struct hal_mon_usig_mu mu;
|
|
};
|
|
|
|
struct hal_mon_usig_hdr {
|
|
struct hal_mon_usig_cmn cmn;
|
|
union hal_mon_usig_non_cmn non_cmn;
|
|
} __packed;
|
|
|
|
#define HAL_RX_USR_INFO0_PHY_PPDU_ID GENMASK(15, 0)
|
|
#define HAL_RX_USR_INFO0_USR_RSSI GENMASK(23, 16)
|
|
#define HAL_RX_USR_INFO0_PKT_TYPE GENMASK(27, 24)
|
|
#define HAL_RX_USR_INFO0_STBC BIT(28)
|
|
#define HAL_RX_USR_INFO0_RECEPTION_TYPE GENMASK(31, 29)
|
|
|
|
#define HAL_RX_USR_INFO1_MCS GENMASK(3, 0)
|
|
#define HAL_RX_USR_INFO1_SGI GENMASK(5, 4)
|
|
#define HAL_RX_USR_INFO1_HE_RANGING_NDP BIT(6)
|
|
#define HAL_RX_USR_INFO1_MIMO_SS_BITMAP GENMASK(15, 8)
|
|
#define HAL_RX_USR_INFO1_RX_BW GENMASK(18, 16)
|
|
#define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX GENMASK(31, 24)
|
|
|
|
#define HAL_RX_USR_INFO2_DL_OFDMA_CONTENT_CHAN BIT(0)
|
|
#define HAL_RX_USR_INFO2_NSS GENMASK(10, 8)
|
|
#define HAL_RX_USR_INFO2_STREAM_OFFSET GENMASK(13, 11)
|
|
#define HAL_RX_USR_INFO2_STA_DCM BIT(14)
|
|
#define HAL_RX_USR_INFO2_LDPC BIT(15)
|
|
#define HAL_RX_USR_INFO2_RU_TYPE_80_0 GENMASK(19, 16)
|
|
#define HAL_RX_USR_INFO2_RU_TYPE_80_1 GENMASK(23, 20)
|
|
#define HAL_RX_USR_INFO2_RU_TYPE_80_2 GENMASK(27, 24)
|
|
#define HAL_RX_USR_INFO2_RU_TYPE_80_3 GENMASK(31, 28)
|
|
|
|
#define HAL_RX_USR_INFO3_RU_START_IDX_80_0 GENMASK(5, 0)
|
|
#define HAL_RX_USR_INFO3_RU_START_IDX_80_1 GENMASK(13, 8)
|
|
#define HAL_RX_USR_INFO3_RU_START_IDX_80_2 GENMASK(21, 16)
|
|
#define HAL_RX_USR_INFO3_RU_START_IDX_80_3 GENMASK(29, 24)
|
|
|
|
struct hal_receive_user_info {
|
|
__le32 info0;
|
|
__le32 info1;
|
|
__le32 info2;
|
|
__le32 info3;
|
|
__le32 user_fd_rssi_seg0;
|
|
__le32 user_fd_rssi_seg1;
|
|
__le32 user_fd_rssi_seg2;
|
|
__le32 user_fd_rssi_seg3;
|
|
} __packed;
|
|
|
|
enum hal_mon_reception_type {
|
|
HAL_RECEPTION_TYPE_SU,
|
|
HAL_RECEPTION_TYPE_DL_MU_MIMO,
|
|
HAL_RECEPTION_TYPE_DL_MU_OFMA,
|
|
HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
|
|
HAL_RECEPTION_TYPE_UL_MU_MIMO,
|
|
HAL_RECEPTION_TYPE_UL_MU_OFDMA,
|
|
HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
|
|
};
|
|
|
|
/* Different allowed RU in 11BE */
|
|
#define HAL_EHT_RU_26 0ULL
|
|
#define HAL_EHT_RU_52 1ULL
|
|
#define HAL_EHT_RU_78 2ULL
|
|
#define HAL_EHT_RU_106 3ULL
|
|
#define HAL_EHT_RU_132 4ULL
|
|
#define HAL_EHT_RU_242 5ULL
|
|
#define HAL_EHT_RU_484 6ULL
|
|
#define HAL_EHT_RU_726 7ULL
|
|
#define HAL_EHT_RU_996 8ULL
|
|
#define HAL_EHT_RU_996x2 9ULL
|
|
#define HAL_EHT_RU_996x3 10ULL
|
|
#define HAL_EHT_RU_996x4 11ULL
|
|
#define HAL_EHT_RU_NONE 15ULL
|
|
#define HAL_EHT_RU_INVALID 31ULL
|
|
/* MRUs spanning above 80Mhz
|
|
* HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved)
|
|
*/
|
|
#define HAL_EHT_RU_996_484 18ULL
|
|
#define HAL_EHT_RU_996x2_484 28ULL
|
|
#define HAL_EHT_RU_996x3_484 40ULL
|
|
#define HAL_EHT_RU_996_484_242 23ULL
|
|
|
|
#define NUM_RU_BITS_PER80 16
|
|
#define NUM_RU_BITS_PER20 4
|
|
|
|
/* Different per_80Mhz band in 320Mhz bandwidth */
|
|
#define HAL_80_0 0
|
|
#define HAL_80_1 1
|
|
#define HAL_80_2 2
|
|
#define HAL_80_3 3
|
|
|
|
#define HAL_RU_80MHZ(num_band) ((num_band) * NUM_RU_BITS_PER80)
|
|
#define HAL_RU_20MHZ(idx_per_80) ((idx_per_80) * NUM_RU_BITS_PER20)
|
|
|
|
#define HAL_RU_SHIFT(num_band, idx_per_80) \
|
|
(HAL_RU_80MHZ(num_band) + HAL_RU_20MHZ(idx_per_80))
|
|
|
|
#define HAL_RU(ru, num_band, idx_per_80) \
|
|
((u64)(ru) << HAL_RU_SHIFT(num_band, idx_per_80))
|
|
|
|
/* MRU-996+484 */
|
|
#define HAL_EHT_RU_996_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
|
|
#define HAL_EHT_RU_996_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
|
|
#define HAL_EHT_RU_996_484_2 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1))
|
|
#define HAL_EHT_RU_996_484_3 (HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0))
|
|
#define HAL_EHT_RU_996_484_4 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996_484_5 (HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996_484_6 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
|
|
#define HAL_EHT_RU_996_484_7 (HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
|
|
|
|
/* MRU-996x2+484 */
|
|
#define HAL_EHT_RU_996x2_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
|
|
#define HAL_EHT_RU_996x2_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
|
|
#define HAL_EHT_RU_996x2_484_2 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
|
|
#define HAL_EHT_RU_996x2_484_3 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
|
|
#define HAL_EHT_RU_996x2_484_4 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1))
|
|
#define HAL_EHT_RU_996x2_484_5 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0))
|
|
#define HAL_EHT_RU_996x2_484_6 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x2_484_7 (HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x2_484_8 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x2_484_9 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x2_484_10 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
|
|
#define HAL_EHT_RU_996x2_484_11 (HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
|
|
|
|
/* MRU-996x3+484 */
|
|
#define HAL_EHT_RU_996x3_484_0 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_1 (HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_2 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_3 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_4 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_5 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
|
|
#define HAL_EHT_RU_996x3_484_6 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
|
|
#define HAL_EHT_RU_996x3_484_7 (HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) | \
|
|
HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) | \
|
|
HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
|
|
|
|
#define HAL_RU_PER80(ru_per80, num_80mhz, ru_idx_per80mhz) \
|
|
(HAL_RU(ru_per80, num_80mhz, ru_idx_per80mhz))
|
|
|
|
#define RU_INVALID 0
|
|
#define RU_26 1
|
|
#define RU_52 2
|
|
#define RU_106 4
|
|
#define RU_242 9
|
|
#define RU_484 18
|
|
#define RU_996 37
|
|
#define RU_2X996 74
|
|
#define RU_3X996 111
|
|
#define RU_4X996 148
|
|
#define RU_52_26 (RU_52 + RU_26)
|
|
#define RU_106_26 (RU_106 + RU_26)
|
|
#define RU_484_242 (RU_484 + RU_242)
|
|
#define RU_996_484 (RU_996 + RU_484)
|
|
#define RU_996_484_242 (RU_996 + RU_484_242)
|
|
#define RU_2X996_484 (RU_2X996 + RU_484)
|
|
#define RU_3X996_484 (RU_3X996 + RU_484)
|
|
|
|
enum ath12k_eht_ru_size {
|
|
ATH12K_EHT_RU_26,
|
|
ATH12K_EHT_RU_52,
|
|
ATH12K_EHT_RU_106,
|
|
ATH12K_EHT_RU_242,
|
|
ATH12K_EHT_RU_484,
|
|
ATH12K_EHT_RU_996,
|
|
ATH12K_EHT_RU_996x2,
|
|
ATH12K_EHT_RU_996x4,
|
|
ATH12K_EHT_RU_52_26,
|
|
ATH12K_EHT_RU_106_26,
|
|
ATH12K_EHT_RU_484_242,
|
|
ATH12K_EHT_RU_996_484,
|
|
ATH12K_EHT_RU_996_484_242,
|
|
ATH12K_EHT_RU_996x2_484,
|
|
ATH12K_EHT_RU_996x3,
|
|
ATH12K_EHT_RU_996x3_484,
|
|
|
|
/* Keep last */
|
|
ATH12K_EHT_RU_INVALID,
|
|
};
|
|
|
|
#define HAL_RX_RU_ALLOC_TYPE_MAX ATH12K_EHT_RU_INVALID
|
|
|
|
static inline
|
|
enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
|
|
{
|
|
enum nl80211_he_ru_alloc ret;
|
|
|
|
switch (ru_tones) {
|
|
case RU_52:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
|
|
break;
|
|
case RU_106:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
|
|
break;
|
|
case RU_242:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
|
|
break;
|
|
case RU_484:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
|
|
break;
|
|
case RU_996:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
|
|
break;
|
|
case RU_2X996:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
|
|
break;
|
|
case RU_26:
|
|
fallthrough;
|
|
default:
|
|
ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
|
|
struct hal_tlv_64_hdr *tlv,
|
|
struct hal_reo_status *status);
|
|
void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
|
|
u32 *msdu_cookies,
|
|
enum hal_rx_buf_return_buf_manager *rbm);
|
|
void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
|
|
struct hal_wbm_release_ring *desc,
|
|
struct ath12k_buffer_addr *buf_addr_info,
|
|
enum hal_wbm_rel_bm_act action);
|
|
void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
|
|
dma_addr_t paddr, u32 cookie, u8 manager);
|
|
void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
|
|
dma_addr_t *paddr,
|
|
u32 *cookie, u8 *rbm);
|
|
int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
|
|
struct hal_reo_dest_ring *desc,
|
|
dma_addr_t *paddr, u32 *desc_bank);
|
|
int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
|
|
struct hal_rx_wbm_rel_info *rel_info);
|
|
void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
|
|
struct ath12k_buffer_addr *buff_addr,
|
|
dma_addr_t *paddr, u32 *cookie);
|
|
void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, u32 *sw_cookie,
|
|
struct ath12k_buffer_addr **pp_buf_addr,
|
|
u8 *rbm, u32 *msdu_cnt);
|
|
void ath12k_hal_rx_msdu_list_get(struct ath12k *ar,
|
|
struct hal_rx_msdu_link *link_desc,
|
|
struct hal_rx_msdu_list *msdu_list,
|
|
u16 *num_msdus);
|
|
|
|
#endif
|