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be378ebd6c
Move some macros to phy-lib because MediaTek's 2.5G built-in ethernet PHY will also use them. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
142 lines
4.4 KiB
C
142 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include "mtk.h"
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#define MTK_GPHY_ID_MT7530 0x03a29412
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#define MTK_GPHY_ID_MT7531 0x03a29441
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#define MTK_PHY_PAGE_EXTENDED_2 0x0002
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#define MTK_PHY_PAGE_EXTENDED_3 0x0003
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#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
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#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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/* Registers on Token Ring debug nodes */
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/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
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#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
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/* Registers on MDIO_MMD_VEND1 */
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#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
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#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
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#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
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#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
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#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
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#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
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#define MTK_PHY_RXADC_CTRL_RG7 0xc6
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#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
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#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
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#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
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#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
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static void mtk_gephy_config_init(struct phy_device *phydev)
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{
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/* Enable HW auto downshift */
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phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
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MTK_PHY_AUX_CTRL_AND_STATUS,
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0, MTK_PHY_ENABLE_DOWNSHIFT);
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/* Increase SlvDPSready time */
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mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
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FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
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/* Adjust 100_mse_threshold */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
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MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
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MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
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FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
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0xff) |
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FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
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0xff));
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/* If echo time is narrower than 0x3, it will be regarded as noise */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
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MTK_MCC_NEARECHO_OFFSET_MASK,
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FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
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}
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static int mt7530_phy_config_init(struct phy_device *phydev)
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{
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mtk_gephy_config_init(phydev);
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/* Increase post_update_timer */
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phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
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MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
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return 0;
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}
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static int mt7531_phy_config_init(struct phy_device *phydev)
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{
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mtk_gephy_config_init(phydev);
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/* PHY link down power saving enable */
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phy_set_bits(phydev, 0x17, BIT(4));
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
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MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
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FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
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/* Set TX Pair delay selection */
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
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MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
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FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
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FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
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phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
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MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
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FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
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FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
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return 0;
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}
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static struct phy_driver mtk_gephy_driver[] = {
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{
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
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.name = "MediaTek MT7530 PHY",
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.config_init = mt7530_phy_config_init,
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/* Interrupts are handled by the switch, not the PHY
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* itself.
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*/
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.config_intr = genphy_no_config_intr,
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.handle_interrupt = genphy_handle_interrupt_no_ack,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = mtk_phy_read_page,
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.write_page = mtk_phy_write_page,
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},
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{
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
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.name = "MediaTek MT7531 PHY",
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.config_init = mt7531_phy_config_init,
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/* Interrupts are handled by the switch, not the PHY
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* itself.
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*/
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.config_intr = genphy_no_config_intr,
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.handle_interrupt = genphy_handle_interrupt_no_ack,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = mtk_phy_read_page,
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.write_page = mtk_phy_write_page,
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},
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};
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module_phy_driver(mtk_gephy_driver);
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static const struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
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{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
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{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
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{ }
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};
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MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
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MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
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