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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00

For NGBE devices, the queue number is limited to be 1 when SRIOV is
enabled. In this case, IRQ vector[0] is used for MISC and vector[1] is
used for queue, based on the previous patches. But for the hardware
design, the IRQ vector[1] must be allocated for use by the VF[6] when
the number of VFs is 7. So the IRQ vector[0] should be shared for PF
MISC and QUEUE interrupts.
+-----------+----------------------+
| Vector | Assigned To |
+-----------+----------------------+
| Vector 0 | PF MISC and QUEUE |
| Vector 1 | VF 6 |
| Vector 2 | VF 5 |
| Vector 3 | VF 4 |
| Vector 4 | VF 3 |
| Vector 5 | VF 2 |
| Vector 6 | VF 1 |
| Vector 7 | VF 0 |
+-----------+----------------------+
Minimize code modifications, only adjust the IRQ vector number for this
case.
Fixes: 877253d2cb
("net: ngbe: add sriov function support")
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com>
Link: https://patch.msgid.link/20250701063030.59340-4-jiawenwu@trustnetic.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
913 lines
22 KiB
C
913 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include "wx_type.h"
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#include "wx_hw.h"
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#include "wx_mbx.h"
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#include "wx_sriov.h"
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static void wx_vf_configuration(struct pci_dev *pdev, int event_mask)
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{
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bool enable = !!WX_VF_ENABLE_CHECK(event_mask);
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struct wx *wx = pci_get_drvdata(pdev);
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u32 vfn = WX_VF_NUM_GET(event_mask);
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if (enable)
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eth_zero_addr(wx->vfinfo[vfn].vf_mac_addr);
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}
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static int wx_alloc_vf_macvlans(struct wx *wx, u8 num_vfs)
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{
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struct vf_macvlans *mv_list;
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int num_vf_macvlans, i;
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/* Initialize list of VF macvlans */
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INIT_LIST_HEAD(&wx->vf_mvs.mvlist);
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num_vf_macvlans = wx->mac.num_rar_entries -
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(WX_MAX_PF_MACVLANS + 1 + num_vfs);
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if (!num_vf_macvlans)
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return -EINVAL;
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mv_list = kcalloc(num_vf_macvlans, sizeof(struct vf_macvlans),
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GFP_KERNEL);
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if (!mv_list)
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return -ENOMEM;
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for (i = 0; i < num_vf_macvlans; i++) {
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mv_list[i].vf = -1;
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mv_list[i].free = true;
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list_add(&mv_list[i].mvlist, &wx->vf_mvs.mvlist);
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}
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wx->mv_list = mv_list;
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return 0;
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}
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static void wx_sriov_clear_data(struct wx *wx)
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{
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/* set num VFs to 0 to prevent access to vfinfo */
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wx->num_vfs = 0;
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/* free VF control structures */
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kfree(wx->vfinfo);
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wx->vfinfo = NULL;
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/* free macvlan list */
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kfree(wx->mv_list);
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wx->mv_list = NULL;
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/* set default pool back to 0 */
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wr32m(wx, WX_PSR_VM_CTL, WX_PSR_VM_CTL_POOL_MASK, 0);
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wx->ring_feature[RING_F_VMDQ].offset = 0;
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clear_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
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clear_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
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/* Disable VMDq flag so device will be set in NM mode */
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if (wx->ring_feature[RING_F_VMDQ].limit == 1)
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clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags);
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}
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static int __wx_enable_sriov(struct wx *wx, u8 num_vfs)
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{
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int i, ret = 0;
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u32 value = 0;
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set_bit(WX_FLAG_SRIOV_ENABLED, wx->flags);
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dev_info(&wx->pdev->dev, "SR-IOV enabled with %d VFs\n", num_vfs);
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if (num_vfs == 7 && wx->mac.type == wx_mac_em)
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set_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags);
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/* Enable VMDq flag so device will be set in VM mode */
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set_bit(WX_FLAG_VMDQ_ENABLED, wx->flags);
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if (!wx->ring_feature[RING_F_VMDQ].limit)
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wx->ring_feature[RING_F_VMDQ].limit = 1;
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wx->ring_feature[RING_F_VMDQ].offset = num_vfs;
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wx->vfinfo = kcalloc(num_vfs, sizeof(struct vf_data_storage),
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GFP_KERNEL);
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if (!wx->vfinfo)
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return -ENOMEM;
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ret = wx_alloc_vf_macvlans(wx, num_vfs);
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if (ret)
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return ret;
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/* Initialize default switching mode VEB */
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wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_SW_EN, WX_PSR_CTL_SW_EN);
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for (i = 0; i < num_vfs; i++) {
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/* enable spoof checking for all VFs */
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wx->vfinfo[i].spoofchk_enabled = true;
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wx->vfinfo[i].link_enable = true;
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/* untrust all VFs */
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wx->vfinfo[i].trusted = false;
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/* set the default xcast mode */
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wx->vfinfo[i].xcast_mode = WXVF_XCAST_MODE_NONE;
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}
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if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) {
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value = WX_CFG_PORT_CTL_NUM_VT_8;
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} else {
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if (num_vfs < 32)
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value = WX_CFG_PORT_CTL_NUM_VT_32;
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else
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value = WX_CFG_PORT_CTL_NUM_VT_64;
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}
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wr32m(wx, WX_CFG_PORT_CTL,
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WX_CFG_PORT_CTL_NUM_VT_MASK,
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value);
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return ret;
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}
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static void wx_sriov_reinit(struct wx *wx)
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{
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rtnl_lock();
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wx->setup_tc(wx->netdev, netdev_get_num_tc(wx->netdev));
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rtnl_unlock();
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}
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void wx_disable_sriov(struct wx *wx)
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{
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if (!pci_vfs_assigned(wx->pdev))
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pci_disable_sriov(wx->pdev);
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else
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wx_err(wx, "Unloading driver while VFs are assigned.\n");
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/* clear flags and free allloced data */
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wx_sriov_clear_data(wx);
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}
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EXPORT_SYMBOL(wx_disable_sriov);
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static int wx_pci_sriov_enable(struct pci_dev *dev,
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int num_vfs)
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{
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struct wx *wx = pci_get_drvdata(dev);
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int err = 0, i;
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err = __wx_enable_sriov(wx, num_vfs);
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if (err)
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return err;
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wx->num_vfs = num_vfs;
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for (i = 0; i < wx->num_vfs; i++)
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wx_vf_configuration(dev, (i | WX_VF_ENABLE));
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/* reset before enabling SRIOV to avoid mailbox issues */
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wx_sriov_reinit(wx);
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err = pci_enable_sriov(dev, num_vfs);
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if (err) {
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wx_err(wx, "Failed to enable PCI sriov: %d\n", err);
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goto err_out;
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}
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return num_vfs;
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err_out:
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wx_sriov_clear_data(wx);
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return err;
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}
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static void wx_pci_sriov_disable(struct pci_dev *dev)
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{
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struct wx *wx = pci_get_drvdata(dev);
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wx_disable_sriov(wx);
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wx_sriov_reinit(wx);
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}
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int wx_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
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{
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struct wx *wx = pci_get_drvdata(pdev);
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int err;
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if (!num_vfs) {
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if (!pci_vfs_assigned(pdev)) {
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wx_pci_sriov_disable(pdev);
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return 0;
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}
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wx_err(wx, "can't free VFs because some are assigned to VMs.\n");
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return -EBUSY;
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}
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err = wx_pci_sriov_enable(pdev, num_vfs);
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if (err)
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return err;
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return num_vfs;
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}
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EXPORT_SYMBOL(wx_pci_sriov_configure);
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static int wx_set_vf_mac(struct wx *wx, u16 vf, const u8 *mac_addr)
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{
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u8 hw_addr[ETH_ALEN];
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int ret = 0;
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ether_addr_copy(hw_addr, mac_addr);
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wx_del_mac_filter(wx, wx->vfinfo[vf].vf_mac_addr, vf);
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ret = wx_add_mac_filter(wx, hw_addr, vf);
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if (ret >= 0)
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ether_addr_copy(wx->vfinfo[vf].vf_mac_addr, mac_addr);
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else
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eth_zero_addr(wx->vfinfo[vf].vf_mac_addr);
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return ret;
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}
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static void wx_set_vmolr(struct wx *wx, u16 vf, bool aupe)
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{
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u32 vmolr = rd32(wx, WX_PSR_VM_L2CTL(vf));
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vmolr |= WX_PSR_VM_L2CTL_BAM;
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if (aupe)
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vmolr |= WX_PSR_VM_L2CTL_AUPE;
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else
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vmolr &= ~WX_PSR_VM_L2CTL_AUPE;
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wr32(wx, WX_PSR_VM_L2CTL(vf), vmolr);
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}
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static void wx_set_vmvir(struct wx *wx, u16 vid, u16 qos, u16 vf)
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{
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u32 vmvir = vid | (qos << VLAN_PRIO_SHIFT) |
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WX_TDM_VLAN_INS_VLANA_DEFAULT;
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wr32(wx, WX_TDM_VLAN_INS(vf), vmvir);
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}
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static int wx_set_vf_vlan(struct wx *wx, int add, int vid, u16 vf)
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{
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if (!vid && !add)
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return 0;
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return wx_set_vfta(wx, vid, vf, (bool)add);
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}
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static void wx_set_vlan_anti_spoofing(struct wx *wx, bool enable, int vf)
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{
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u32 index = WX_VF_REG_OFFSET(vf), vf_bit = WX_VF_IND_SHIFT(vf);
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u32 pfvfspoof;
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pfvfspoof = rd32(wx, WX_TDM_VLAN_AS(index));
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if (enable)
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pfvfspoof |= BIT(vf_bit);
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else
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pfvfspoof &= ~BIT(vf_bit);
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wr32(wx, WX_TDM_VLAN_AS(index), pfvfspoof);
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}
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static void wx_write_qde(struct wx *wx, u32 vf, u32 qde)
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{
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struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ];
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u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
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u32 reg = 0, n = vf * q_per_pool / 32;
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u32 i = vf * q_per_pool;
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reg = rd32(wx, WX_RDM_PF_QDE(n));
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for (i = (vf * q_per_pool - n * 32);
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i < ((vf + 1) * q_per_pool - n * 32);
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i++) {
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if (qde == 1)
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reg |= qde << i;
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else
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reg &= qde << i;
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}
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wr32(wx, WX_RDM_PF_QDE(n), reg);
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}
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static void wx_clear_vmvir(struct wx *wx, u32 vf)
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{
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wr32(wx, WX_TDM_VLAN_INS(vf), 0);
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}
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static void wx_ping_vf(struct wx *wx, int vf)
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{
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u32 ping = WX_PF_CONTROL_MSG;
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if (wx->vfinfo[vf].clear_to_send)
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ping |= WX_VT_MSGTYPE_CTS;
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wx_write_mbx_pf(wx, &ping, 1, vf);
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}
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static void wx_set_vf_rx_tx(struct wx *wx, int vf)
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{
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u32 index = WX_VF_REG_OFFSET(vf), vf_bit = WX_VF_IND_SHIFT(vf);
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u32 reg_cur_tx, reg_cur_rx, reg_req_tx, reg_req_rx;
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reg_cur_tx = rd32(wx, WX_TDM_VF_TE(index));
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reg_cur_rx = rd32(wx, WX_RDM_VF_RE(index));
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if (wx->vfinfo[vf].link_enable) {
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reg_req_tx = reg_cur_tx | BIT(vf_bit);
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reg_req_rx = reg_cur_rx | BIT(vf_bit);
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/* Enable particular VF */
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if (reg_cur_tx != reg_req_tx)
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wr32(wx, WX_TDM_VF_TE(index), reg_req_tx);
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if (reg_cur_rx != reg_req_rx)
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wr32(wx, WX_RDM_VF_RE(index), reg_req_rx);
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} else {
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reg_req_tx = BIT(vf_bit);
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reg_req_rx = BIT(vf_bit);
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/* Disable particular VF */
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if (reg_cur_tx & reg_req_tx)
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wr32(wx, WX_TDM_VFTE_CLR(index), reg_req_tx);
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if (reg_cur_rx & reg_req_rx)
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wr32(wx, WX_RDM_VFRE_CLR(index), reg_req_rx);
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}
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}
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static int wx_get_vf_queues(struct wx *wx, u32 *msgbuf, u32 vf)
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{
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struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ];
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unsigned int default_tc = 0;
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msgbuf[WX_VF_TX_QUEUES] = __ALIGN_MASK(1, ~vmdq->mask);
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msgbuf[WX_VF_RX_QUEUES] = __ALIGN_MASK(1, ~vmdq->mask);
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if (wx->vfinfo[vf].pf_vlan || wx->vfinfo[vf].pf_qos)
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msgbuf[WX_VF_TRANS_VLAN] = 1;
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else
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msgbuf[WX_VF_TRANS_VLAN] = 0;
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/* notify VF of default queue */
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msgbuf[WX_VF_DEF_QUEUE] = default_tc;
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return 0;
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}
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static void wx_vf_reset_event(struct wx *wx, u16 vf)
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{
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struct vf_data_storage *vfinfo = &wx->vfinfo[vf];
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u8 num_tcs = netdev_get_num_tc(wx->netdev);
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/* add PF assigned VLAN */
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wx_set_vf_vlan(wx, true, vfinfo->pf_vlan, vf);
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/* reset offloads to defaults */
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wx_set_vmolr(wx, vf, !vfinfo->pf_vlan);
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/* set outgoing tags for VFs */
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if (!vfinfo->pf_vlan && !vfinfo->pf_qos && !num_tcs) {
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wx_clear_vmvir(wx, vf);
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} else {
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if (vfinfo->pf_qos || !num_tcs)
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wx_set_vmvir(wx, vfinfo->pf_vlan,
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vfinfo->pf_qos, vf);
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else
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wx_set_vmvir(wx, vfinfo->pf_vlan,
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wx->default_up, vf);
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}
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/* reset multicast table array for vf */
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wx->vfinfo[vf].num_vf_mc_hashes = 0;
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/* Flush and reset the mta with the new values */
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wx_set_rx_mode(wx->netdev);
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wx_del_mac_filter(wx, wx->vfinfo[vf].vf_mac_addr, vf);
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/* reset VF api back to unknown */
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wx->vfinfo[vf].vf_api = wx_mbox_api_null;
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}
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static void wx_vf_reset_msg(struct wx *wx, u16 vf)
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{
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const u8 *vf_mac = wx->vfinfo[vf].vf_mac_addr;
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struct net_device *dev = wx->netdev;
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u32 msgbuf[5] = {0, 0, 0, 0, 0};
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u8 *addr = (u8 *)(&msgbuf[1]);
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u32 reg = 0, index, vf_bit;
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int pf_max_frame;
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/* reset the filters for the device */
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wx_vf_reset_event(wx, vf);
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/* set vf mac address */
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if (!is_zero_ether_addr(vf_mac))
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wx_set_vf_mac(wx, vf, vf_mac);
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index = WX_VF_REG_OFFSET(vf);
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vf_bit = WX_VF_IND_SHIFT(vf);
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/* force drop enable for all VF Rx queues */
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wx_write_qde(wx, vf, 1);
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/* set transmit and receive for vf */
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wx_set_vf_rx_tx(wx, vf);
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pf_max_frame = dev->mtu + ETH_HLEN;
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if (pf_max_frame > ETH_FRAME_LEN)
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reg = BIT(vf_bit);
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wr32(wx, WX_RDM_VFRE_CLR(index), reg);
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/* enable VF mailbox for further messages */
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wx->vfinfo[vf].clear_to_send = true;
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/* reply to reset with ack and vf mac address */
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msgbuf[0] = WX_VF_RESET;
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if (!is_zero_ether_addr(vf_mac)) {
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msgbuf[0] |= WX_VT_MSGTYPE_ACK;
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memcpy(addr, vf_mac, ETH_ALEN);
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} else {
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msgbuf[0] |= WX_VT_MSGTYPE_NACK;
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wx_err(wx, "VF %d has no MAC address assigned", vf);
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}
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msgbuf[3] = wx->mac.mc_filter_type;
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wx_write_mbx_pf(wx, msgbuf, WX_VF_PERMADDR_MSG_LEN, vf);
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}
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static int wx_set_vf_mac_addr(struct wx *wx, u32 *msgbuf, u16 vf)
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{
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const u8 *new_mac = ((u8 *)(&msgbuf[1]));
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int ret;
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|
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if (!is_valid_ether_addr(new_mac)) {
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wx_err(wx, "VF %d attempted to set invalid mac\n", vf);
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return -EINVAL;
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}
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if (wx->vfinfo[vf].pf_set_mac &&
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memcmp(wx->vfinfo[vf].vf_mac_addr, new_mac, ETH_ALEN)) {
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wx_err(wx,
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"VF %d attempt to set a MAC but it already had a MAC.",
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vf);
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return -EBUSY;
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}
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|
|
ret = wx_set_vf_mac(wx, vf, new_mac);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void wx_set_vf_multicasts(struct wx *wx, u32 *msgbuf, u32 vf)
|
|
{
|
|
struct vf_data_storage *vfinfo = &wx->vfinfo[vf];
|
|
u16 entries = (msgbuf[0] & WX_VT_MSGINFO_MASK)
|
|
>> WX_VT_MSGINFO_SHIFT;
|
|
u32 vmolr = rd32(wx, WX_PSR_VM_L2CTL(vf));
|
|
u32 vector_bit, vector_reg, mta_reg, i;
|
|
u16 *hash_list = (u16 *)&msgbuf[1];
|
|
|
|
/* only so many hash values supported */
|
|
entries = min_t(u16, entries, WX_MAX_VF_MC_ENTRIES);
|
|
vfinfo->num_vf_mc_hashes = entries;
|
|
|
|
for (i = 0; i < entries; i++)
|
|
vfinfo->vf_mc_hashes[i] = hash_list[i];
|
|
|
|
for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
|
|
vector_reg = WX_PSR_MC_TBL_REG(vfinfo->vf_mc_hashes[i]);
|
|
vector_bit = WX_PSR_MC_TBL_BIT(vfinfo->vf_mc_hashes[i]);
|
|
mta_reg = wx->mac.mta_shadow[vector_reg];
|
|
mta_reg |= BIT(vector_bit);
|
|
wx->mac.mta_shadow[vector_reg] = mta_reg;
|
|
wr32(wx, WX_PSR_MC_TBL(vector_reg), mta_reg);
|
|
}
|
|
vmolr |= WX_PSR_VM_L2CTL_ROMPE;
|
|
wr32(wx, WX_PSR_VM_L2CTL(vf), vmolr);
|
|
}
|
|
|
|
static void wx_set_vf_lpe(struct wx *wx, u32 max_frame, u32 vf)
|
|
{
|
|
u32 index, vf_bit, vfre;
|
|
u32 max_frs, reg_val;
|
|
|
|
/* determine VF receive enable location */
|
|
index = WX_VF_REG_OFFSET(vf);
|
|
vf_bit = WX_VF_IND_SHIFT(vf);
|
|
|
|
vfre = rd32(wx, WX_RDM_VF_RE(index));
|
|
vfre |= BIT(vf_bit);
|
|
wr32(wx, WX_RDM_VF_RE(index), vfre);
|
|
|
|
/* pull current max frame size from hardware */
|
|
max_frs = DIV_ROUND_UP(max_frame, 1024);
|
|
reg_val = rd32(wx, WX_MAC_WDG_TIMEOUT) & WX_MAC_WDG_TIMEOUT_WTO_MASK;
|
|
if (max_frs > (reg_val + WX_MAC_WDG_TIMEOUT_WTO_DELTA))
|
|
wr32(wx, WX_MAC_WDG_TIMEOUT,
|
|
max_frs - WX_MAC_WDG_TIMEOUT_WTO_DELTA);
|
|
}
|
|
|
|
static int wx_find_vlvf_entry(struct wx *wx, u32 vlan)
|
|
{
|
|
int regindex;
|
|
u32 vlvf;
|
|
|
|
/* short cut the special case */
|
|
if (vlan == 0)
|
|
return 0;
|
|
|
|
/* Search for the vlan id in the VLVF entries */
|
|
for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) {
|
|
wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex);
|
|
vlvf = rd32(wx, WX_PSR_VLAN_SWC);
|
|
if ((vlvf & VLAN_VID_MASK) == vlan)
|
|
break;
|
|
}
|
|
|
|
/* Return a negative value if not found */
|
|
if (regindex >= WX_PSR_VLAN_SWC_ENTRIES)
|
|
regindex = -EINVAL;
|
|
|
|
return regindex;
|
|
}
|
|
|
|
static int wx_set_vf_macvlan(struct wx *wx,
|
|
u16 vf, int index, unsigned char *mac_addr)
|
|
{
|
|
struct vf_macvlans *entry;
|
|
struct list_head *pos;
|
|
int retval = 0;
|
|
|
|
if (index <= 1) {
|
|
list_for_each(pos, &wx->vf_mvs.mvlist) {
|
|
entry = list_entry(pos, struct vf_macvlans, mvlist);
|
|
if (entry->vf == vf) {
|
|
entry->vf = -1;
|
|
entry->free = true;
|
|
entry->is_macvlan = false;
|
|
wx_del_mac_filter(wx, entry->vf_macvlan, vf);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!index)
|
|
return 0;
|
|
|
|
entry = NULL;
|
|
list_for_each(pos, &wx->vf_mvs.mvlist) {
|
|
entry = list_entry(pos, struct vf_macvlans, mvlist);
|
|
if (entry->free)
|
|
break;
|
|
}
|
|
|
|
if (!entry || !entry->free)
|
|
return -ENOSPC;
|
|
|
|
retval = wx_add_mac_filter(wx, mac_addr, vf);
|
|
if (retval >= 0) {
|
|
entry->free = false;
|
|
entry->is_macvlan = true;
|
|
entry->vf = vf;
|
|
memcpy(entry->vf_macvlan, mac_addr, ETH_ALEN);
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int wx_set_vf_vlan_msg(struct wx *wx, u32 *msgbuf, u16 vf)
|
|
{
|
|
int add = (msgbuf[0] & WX_VT_MSGINFO_MASK) >> WX_VT_MSGINFO_SHIFT;
|
|
int vid = (msgbuf[1] & WX_PSR_VLAN_SWC_VLANID_MASK);
|
|
int ret;
|
|
|
|
if (add)
|
|
wx->vfinfo[vf].vlan_count++;
|
|
else if (wx->vfinfo[vf].vlan_count)
|
|
wx->vfinfo[vf].vlan_count--;
|
|
|
|
/* in case of promiscuous mode any VLAN filter set for a VF must
|
|
* also have the PF pool added to it.
|
|
*/
|
|
if (add && wx->netdev->flags & IFF_PROMISC)
|
|
wx_set_vf_vlan(wx, add, vid, VMDQ_P(0));
|
|
|
|
ret = wx_set_vf_vlan(wx, add, vid, vf);
|
|
if (!ret && wx->vfinfo[vf].spoofchk_enabled)
|
|
wx_set_vlan_anti_spoofing(wx, true, vf);
|
|
|
|
/* Go through all the checks to see if the VLAN filter should
|
|
* be wiped completely.
|
|
*/
|
|
if (!add && wx->netdev->flags & IFF_PROMISC) {
|
|
u32 bits = 0, vlvf;
|
|
int reg_ndx;
|
|
|
|
reg_ndx = wx_find_vlvf_entry(wx, vid);
|
|
if (reg_ndx < 0)
|
|
return -ENOSPC;
|
|
wr32(wx, WX_PSR_VLAN_SWC_IDX, reg_ndx);
|
|
vlvf = rd32(wx, WX_PSR_VLAN_SWC);
|
|
/* See if any other pools are set for this VLAN filter
|
|
* entry other than the PF.
|
|
*/
|
|
if (VMDQ_P(0) < 32) {
|
|
bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L);
|
|
bits &= ~BIT(VMDQ_P(0));
|
|
if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags))
|
|
bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H);
|
|
} else {
|
|
if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags))
|
|
bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H);
|
|
bits &= ~BIT(VMDQ_P(0) % 32);
|
|
bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L);
|
|
}
|
|
/* If the filter was removed then ensure PF pool bit
|
|
* is cleared if the PF only added itself to the pool
|
|
* because the PF is in promiscuous mode.
|
|
*/
|
|
if ((vlvf & VLAN_VID_MASK) == vid && !bits)
|
|
wx_set_vf_vlan(wx, add, vid, VMDQ_P(0));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wx_set_vf_macvlan_msg(struct wx *wx, u32 *msgbuf, u16 vf)
|
|
{
|
|
int index = (msgbuf[0] & WX_VT_MSGINFO_MASK) >>
|
|
WX_VT_MSGINFO_SHIFT;
|
|
u8 *new_mac = ((u8 *)(&msgbuf[1]));
|
|
int err;
|
|
|
|
if (wx->vfinfo[vf].pf_set_mac && index > 0) {
|
|
wx_err(wx, "VF %d request MACVLAN filter but is denied\n", vf);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* An non-zero index indicates the VF is setting a filter */
|
|
if (index) {
|
|
if (!is_valid_ether_addr(new_mac)) {
|
|
wx_err(wx, "VF %d attempted to set invalid mac\n", vf);
|
|
return -EINVAL;
|
|
}
|
|
/* If the VF is allowed to set MAC filters then turn off
|
|
* anti-spoofing to avoid false positives.
|
|
*/
|
|
if (wx->vfinfo[vf].spoofchk_enabled)
|
|
wx_set_vf_spoofchk(wx->netdev, vf, false);
|
|
}
|
|
|
|
err = wx_set_vf_macvlan(wx, vf, index, new_mac);
|
|
if (err == -ENOSPC)
|
|
wx_err(wx,
|
|
"VF %d request MACVLAN filter but there is no space\n",
|
|
vf);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wx_negotiate_vf_api(struct wx *wx, u32 *msgbuf, u32 vf)
|
|
{
|
|
int api = msgbuf[1];
|
|
|
|
switch (api) {
|
|
case wx_mbox_api_13:
|
|
wx->vfinfo[vf].vf_api = api;
|
|
return 0;
|
|
default:
|
|
wx_err(wx, "VF %d requested invalid api version %u\n", vf, api);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int wx_get_vf_link_state(struct wx *wx, u32 *msgbuf, u32 vf)
|
|
{
|
|
msgbuf[1] = wx->vfinfo[vf].link_enable;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wx_get_fw_version(struct wx *wx, u32 *msgbuf, u32 vf)
|
|
{
|
|
unsigned long fw_version = 0ULL;
|
|
int ret = 0;
|
|
|
|
ret = kstrtoul(wx->eeprom_id, 16, &fw_version);
|
|
if (ret)
|
|
return -EOPNOTSUPP;
|
|
msgbuf[1] = fw_version;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wx_update_vf_xcast_mode(struct wx *wx, u32 *msgbuf, u32 vf)
|
|
{
|
|
int xcast_mode = msgbuf[1];
|
|
u32 vmolr, disable, enable;
|
|
|
|
if (wx->vfinfo[vf].xcast_mode == xcast_mode)
|
|
return 0;
|
|
|
|
switch (xcast_mode) {
|
|
case WXVF_XCAST_MODE_NONE:
|
|
disable = WX_PSR_VM_L2CTL_BAM | WX_PSR_VM_L2CTL_ROMPE |
|
|
WX_PSR_VM_L2CTL_MPE | WX_PSR_VM_L2CTL_UPE |
|
|
WX_PSR_VM_L2CTL_VPE;
|
|
enable = 0;
|
|
break;
|
|
case WXVF_XCAST_MODE_MULTI:
|
|
disable = WX_PSR_VM_L2CTL_MPE | WX_PSR_VM_L2CTL_UPE |
|
|
WX_PSR_VM_L2CTL_VPE;
|
|
enable = WX_PSR_VM_L2CTL_BAM | WX_PSR_VM_L2CTL_ROMPE;
|
|
break;
|
|
case WXVF_XCAST_MODE_ALLMULTI:
|
|
disable = WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_VPE;
|
|
enable = WX_PSR_VM_L2CTL_BAM | WX_PSR_VM_L2CTL_ROMPE |
|
|
WX_PSR_VM_L2CTL_MPE;
|
|
break;
|
|
case WXVF_XCAST_MODE_PROMISC:
|
|
disable = 0;
|
|
enable = WX_PSR_VM_L2CTL_BAM | WX_PSR_VM_L2CTL_ROMPE |
|
|
WX_PSR_VM_L2CTL_MPE | WX_PSR_VM_L2CTL_UPE |
|
|
WX_PSR_VM_L2CTL_VPE;
|
|
break;
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
vmolr = rd32(wx, WX_PSR_VM_L2CTL(vf));
|
|
vmolr &= ~disable;
|
|
vmolr |= enable;
|
|
wr32(wx, WX_PSR_VM_L2CTL(vf), vmolr);
|
|
|
|
wx->vfinfo[vf].xcast_mode = xcast_mode;
|
|
msgbuf[1] = xcast_mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void wx_rcv_msg_from_vf(struct wx *wx, u16 vf)
|
|
{
|
|
u16 mbx_size = WX_VXMAILBOX_SIZE;
|
|
u32 msgbuf[WX_VXMAILBOX_SIZE];
|
|
int retval;
|
|
|
|
retval = wx_read_mbx_pf(wx, msgbuf, mbx_size, vf);
|
|
if (retval) {
|
|
wx_err(wx, "Error receiving message from VF\n");
|
|
return;
|
|
}
|
|
|
|
/* this is a message we already processed, do nothing */
|
|
if (msgbuf[0] & (WX_VT_MSGTYPE_ACK | WX_VT_MSGTYPE_NACK))
|
|
return;
|
|
|
|
if (msgbuf[0] == WX_VF_RESET) {
|
|
wx_vf_reset_msg(wx, vf);
|
|
return;
|
|
}
|
|
|
|
/* until the vf completes a virtual function reset it should not be
|
|
* allowed to start any configuration.
|
|
*/
|
|
if (!wx->vfinfo[vf].clear_to_send) {
|
|
msgbuf[0] |= WX_VT_MSGTYPE_NACK;
|
|
wx_write_mbx_pf(wx, msgbuf, 1, vf);
|
|
return;
|
|
}
|
|
|
|
switch ((msgbuf[0] & U16_MAX)) {
|
|
case WX_VF_SET_MAC_ADDR:
|
|
retval = wx_set_vf_mac_addr(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_SET_MULTICAST:
|
|
wx_set_vf_multicasts(wx, msgbuf, vf);
|
|
retval = 0;
|
|
break;
|
|
case WX_VF_SET_VLAN:
|
|
retval = wx_set_vf_vlan_msg(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_SET_LPE:
|
|
wx_set_vf_lpe(wx, msgbuf[1], vf);
|
|
retval = 0;
|
|
break;
|
|
case WX_VF_SET_MACVLAN:
|
|
retval = wx_set_vf_macvlan_msg(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_API_NEGOTIATE:
|
|
retval = wx_negotiate_vf_api(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_GET_QUEUES:
|
|
retval = wx_get_vf_queues(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_GET_LINK_STATE:
|
|
retval = wx_get_vf_link_state(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_GET_FW_VERSION:
|
|
retval = wx_get_fw_version(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_UPDATE_XCAST_MODE:
|
|
retval = wx_update_vf_xcast_mode(wx, msgbuf, vf);
|
|
break;
|
|
case WX_VF_BACKUP:
|
|
break;
|
|
default:
|
|
wx_err(wx, "Unhandled Msg %8.8x\n", msgbuf[0]);
|
|
break;
|
|
}
|
|
|
|
/* notify the VF of the results of what it sent us */
|
|
if (retval)
|
|
msgbuf[0] |= WX_VT_MSGTYPE_NACK;
|
|
else
|
|
msgbuf[0] |= WX_VT_MSGTYPE_ACK;
|
|
|
|
msgbuf[0] |= WX_VT_MSGTYPE_CTS;
|
|
|
|
wx_write_mbx_pf(wx, msgbuf, mbx_size, vf);
|
|
}
|
|
|
|
static void wx_rcv_ack_from_vf(struct wx *wx, u16 vf)
|
|
{
|
|
u32 msg = WX_VT_MSGTYPE_NACK;
|
|
|
|
/* if device isn't clear to send it shouldn't be reading either */
|
|
if (!wx->vfinfo[vf].clear_to_send)
|
|
wx_write_mbx_pf(wx, &msg, 1, vf);
|
|
}
|
|
|
|
void wx_msg_task(struct wx *wx)
|
|
{
|
|
u16 vf;
|
|
|
|
for (vf = 0; vf < wx->num_vfs; vf++) {
|
|
/* process any reset requests */
|
|
if (!wx_check_for_rst_pf(wx, vf))
|
|
wx_vf_reset_event(wx, vf);
|
|
|
|
/* process any messages pending */
|
|
if (!wx_check_for_msg_pf(wx, vf))
|
|
wx_rcv_msg_from_vf(wx, vf);
|
|
|
|
/* process any acks */
|
|
if (!wx_check_for_ack_pf(wx, vf))
|
|
wx_rcv_ack_from_vf(wx, vf);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(wx_msg_task);
|
|
|
|
void wx_disable_vf_rx_tx(struct wx *wx)
|
|
{
|
|
wr32(wx, WX_TDM_VFTE_CLR(0), U32_MAX);
|
|
wr32(wx, WX_RDM_VFRE_CLR(0), U32_MAX);
|
|
if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) {
|
|
wr32(wx, WX_TDM_VFTE_CLR(1), U32_MAX);
|
|
wr32(wx, WX_RDM_VFRE_CLR(1), U32_MAX);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(wx_disable_vf_rx_tx);
|
|
|
|
void wx_ping_all_vfs_with_link_status(struct wx *wx, bool link_up)
|
|
{
|
|
u32 msgbuf[2] = {0, 0};
|
|
u16 i;
|
|
|
|
if (!wx->num_vfs)
|
|
return;
|
|
msgbuf[0] = WX_PF_NOFITY_VF_LINK_STATUS | WX_PF_CONTROL_MSG;
|
|
if (link_up)
|
|
msgbuf[1] = FIELD_PREP(GENMASK(31, 1), wx->speed) | link_up;
|
|
if (wx->notify_down)
|
|
msgbuf[1] |= WX_PF_NOFITY_VF_NET_NOT_RUNNING;
|
|
for (i = 0; i < wx->num_vfs; i++) {
|
|
if (wx->vfinfo[i].clear_to_send)
|
|
msgbuf[0] |= WX_VT_MSGTYPE_CTS;
|
|
wx_write_mbx_pf(wx, msgbuf, 2, i);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(wx_ping_all_vfs_with_link_status);
|
|
|
|
static void wx_set_vf_link_state(struct wx *wx, int vf, int state)
|
|
{
|
|
wx->vfinfo[vf].link_state = state;
|
|
switch (state) {
|
|
case IFLA_VF_LINK_STATE_AUTO:
|
|
if (netif_running(wx->netdev))
|
|
wx->vfinfo[vf].link_enable = true;
|
|
else
|
|
wx->vfinfo[vf].link_enable = false;
|
|
break;
|
|
case IFLA_VF_LINK_STATE_ENABLE:
|
|
wx->vfinfo[vf].link_enable = true;
|
|
break;
|
|
case IFLA_VF_LINK_STATE_DISABLE:
|
|
wx->vfinfo[vf].link_enable = false;
|
|
break;
|
|
}
|
|
/* restart the VF */
|
|
wx->vfinfo[vf].clear_to_send = false;
|
|
wx_ping_vf(wx, vf);
|
|
|
|
wx_set_vf_rx_tx(wx, vf);
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}
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|
|
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void wx_set_all_vfs(struct wx *wx)
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|
{
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int i;
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|
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for (i = 0; i < wx->num_vfs; i++)
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wx_set_vf_link_state(wx, i, wx->vfinfo[i].link_state);
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}
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EXPORT_SYMBOL(wx_set_all_vfs);
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