mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
6e86fb73de
Fixes overlapping buffer allocation for ICSSG peripheral
used for storing packets to be received/transmitted.
There are 3 buffers:
1. Buffer for Locally Injected Packets
2. Buffer for Forwarding Packets
3. Buffer for Host Egress Packets
In existing allocation buffers for 2. and 3. are overlapping causing
packet corruption.
Packet corruption observations:
During tcp iperf testing, due to overlapping buffers the received ack
packet overwrites the packet to be transmitted. So, we see packets on
wire with the ack packet content inside the content of next TCP packet
from sender device.
Details for AM64x switch mode:
-> Allocation by existing driver:
+---------+-------------------------------------------------------------+
| | SLICE 0 | SLICE 1 |
| +------+--------------+--------+------+--------------+--------+
| | Slot | Base Address | Size | Slot | Base Address | Size |
|---------+------+--------------+--------+------+--------------+--------+
| | 0 | 70000000 | 0x2000 | 0 | 70010000 | 0x2000 |
| | 1 | 70002000 | 0x2000 | 1 | 70012000 | 0x2000 |
| | 2 | 70004000 | 0x2000 | 2 | 70014000 | 0x2000 |
| FWD | 3 | 70006000 | 0x2000 | 3 | 70016000 | 0x2000 |
| Buffers | 4 | 70008000 | 0x2000 | 4 | 70018000 | 0x2000 |
| | 5 | 7000A000 | 0x2000 | 5 | 7001A000 | 0x2000 |
| | 6 | 7000C000 | 0x2000 | 6 | 7001C000 | 0x2000 |
| | 7 | 7000E000 | 0x2000 | 7 | 7001E000 | 0x2000 |
+---------+------+--------------+--------+------+--------------+--------+
| | 8 | 70020000 | 0x1000 | 8 | 70028000 | 0x1000 |
| | 9 | 70021000 | 0x1000 | 9 | 70029000 | 0x1000 |
| | 10 | 70022000 | 0x1000 | 10 | 7002A000 | 0x1000 |
| Our | 11 | 70023000 | 0x1000 | 11 | 7002B000 | 0x1000 |
| LI | 12 | 00000000 | 0x0 | 12 | 00000000 | 0x0 |
| Buffers | 13 | 00000000 | 0x0 | 13 | 00000000 | 0x0 |
| | 14 | 00000000 | 0x0 | 14 | 00000000 | 0x0 |
| | 15 | 00000000 | 0x0 | 15 | 00000000 | 0x0 |
+---------+------+--------------+--------+------+--------------+--------+
| | 16 | 70024000 | 0x1000 | 16 | 7002C000 | 0x1000 |
| | 17 | 70025000 | 0x1000 | 17 | 7002D000 | 0x1000 |
| | 18 | 70026000 | 0x1000 | 18 | 7002E000 | 0x1000 |
| Their | 19 | 70027000 | 0x1000 | 19 | 7002F000 | 0x1000 |
| LI | 20 | 00000000 | 0x0 | 20 | 00000000 | 0x0 |
| Buffers | 21 | 00000000 | 0x0 | 21 | 00000000 | 0x0 |
| | 22 | 00000000 | 0x0 | 22 | 00000000 | 0x0 |
| | 23 | 00000000 | 0x0 | 23 | 00000000 | 0x0 |
+---------+------+--------------+--------+------+--------------+--------+
--> here 16, 17, 18, 19 overlapping with below express buffer
+-----+-----------------------------------------------+
| | SLICE 0 | SLICE 1 |
| +------------+----------+------------+----------+
| | Start addr | End addr | Start addr | End addr |
+-----+------------+----------+------------+----------+
| EXP | 70024000 | 70028000 | 7002C000 | 70030000 | <-- Overlapping
| PRE | 70030000 | 70033800 | 70034000 | 70037800 |
+-----+------------+----------+------------+----------+
+---------------------+----------+----------+
| | SLICE 0 | SLICE 1 |
+---------------------+----------+----------+
| Default Drop Offset | 00000000 | 00000000 | <-- Field not configured
+---------------------+----------+----------+
-> Allocation this patch brings:
+---------+-------------------------------------------------------------+
| | SLICE 0 | SLICE 1 |
| +------+--------------+--------+------+--------------+--------+
| | Slot | Base Address | Size | Slot | Base Address | Size |
|---------+------+--------------+--------+------+--------------+--------+
| | 0 | 70000000 | 0x2000 | 0 | 70040000 | 0x2000 |
| | 1 | 70002000 | 0x2000 | 1 | 70042000 | 0x2000 |
| | 2 | 70004000 | 0x2000 | 2 | 70044000 | 0x2000 |
| FWD | 3 | 70006000 | 0x2000 | 3 | 70046000 | 0x2000 |
| Buffers | 4 | 70008000 | 0x2000 | 4 | 70048000 | 0x2000 |
| | 5 | 7000A000 | 0x2000 | 5 | 7004A000 | 0x2000 |
| | 6 | 7000C000 | 0x2000 | 6 | 7004C000 | 0x2000 |
| | 7 | 7000E000 | 0x2000 | 7 | 7004E000 | 0x2000 |
+---------+------+--------------+--------+------+--------------+--------+
| | 8 | 70010000 | 0x1000 | 8 | 70050000 | 0x1000 |
| | 9 | 70011000 | 0x1000 | 9 | 70051000 | 0x1000 |
| | 10 | 70012000 | 0x1000 | 10 | 70052000 | 0x1000 |
| Our | 11 | 70013000 | 0x1000 | 11 | 70053000 | 0x1000 |
| LI | 12 | 00000000 | 0x0 | 12 | 00000000 | 0x0 |
| Buffers | 13 | 00000000 | 0x0 | 13 | 00000000 | 0x0 |
| | 14 | 00000000 | 0x0 | 14 | 00000000 | 0x0 |
| | 15 | 00000000 | 0x0 | 15 | 00000000 | 0x0 |
+---------+------+--------------+--------+------+--------------+--------+
| | 16 | 70014000 | 0x1000 | 16 | 70054000 | 0x1000 |
| | 17 | 70015000 | 0x1000 | 17 | 70055000 | 0x1000 |
| | 18 | 70016000 | 0x1000 | 18 | 70056000 | 0x1000 |
| Their | 19 | 70017000 | 0x1000 | 19 | 70057000 | 0x1000 |
| LI | 20 | 00000000 | 0x0 | 20 | 00000000 | 0x0 |
| Buffers | 21 | 00000000 | 0x0 | 21 | 00000000 | 0x0 |
| | 22 | 00000000 | 0x0 | 22 | 00000000 | 0x0 |
| | 23 | 00000000 | 0x0 | 23 | 00000000 | 0x0 |
+---------+------+--------------+--------+------+--------------+--------+
+-----+-----------------------------------------------+
| | SLICE 0 | SLICE 1 |
| +------------+----------+------------+----------+
| | Start addr | End addr | Start addr | End addr |
+-----+------------+----------+------------+----------+
| EXP | 70018000 | 7001C000 | 70058000 | 7005C000 |
| PRE | 7001C000 | 7001F800 | 7005C000 | 7005F800 |
+-----+------------+----------+------------+----------+
+---------------------+----------+----------+
| | SLICE 0 | SLICE 1 |
+---------------------+----------+----------+
| Default Drop Offset | 7001F800 | 7005F800 |
+---------------------+----------+----------+
Rootcause: missing buffer configuration for Express frames in
function: prueth_fw_offload_buffer_setup()
Details:
Driver implements two distinct buffer configuration functions that are
invoked based on the driver state and ICSSG firmware:-
- prueth_fw_offload_buffer_setup()
- prueth_emac_buffer_setup()
During initialization, driver creates standard network interfaces
(netdevs) and configures buffers via prueth_emac_buffer_setup().
This function properly allocates and configures all required memory
regions including:
- LI buffers
- Express packet buffers
- Preemptible packet buffers
However, when the driver transitions to an offload mode (switch/HSR/PRP),
buffer reconfiguration is handled by prueth_fw_offload_buffer_setup().
This function does not reconfigure the buffer regions required for
Express packets, leading to incorrect buffer allocation.
Fixes: abd5576b9c ("net: ti: icssg-prueth: Add support for ICSSG switch firmware")
Signed-off-by: Himanshu Mittal <h-mittal1@ti.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250717094220.546388-1-h-mittal1@ti.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
270 lines
9.8 KiB
C
270 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/* Texas Instruments ICSSG Ethernet driver
|
|
*
|
|
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
|
*
|
|
*/
|
|
|
|
#ifndef __NET_TI_ICSSG_SWITCH_MAP_H
|
|
#define __NET_TI_ICSSG_SWITCH_MAP_H
|
|
|
|
/************************* Ethernet Switch Constants *********************/
|
|
|
|
/* if bucket size is changed in firmware then this too should be changed
|
|
* because it directly impacts FDB ageing calculation
|
|
*/
|
|
#define NUMBER_OF_FDB_BUCKET_ENTRIES (4)
|
|
|
|
/* This is fixed in ICSSG */
|
|
#define SIZE_OF_FDB (2048)
|
|
|
|
#define FW_LINK_SPEED_1G (0x00)
|
|
#define FW_LINK_SPEED_100M (0x01)
|
|
#define FW_LINK_SPEED_10M (0x02)
|
|
#define FW_LINK_SPEED_HD (0x80)
|
|
|
|
/* Time after which FDB entries are checked for aged out values.
|
|
* Values are in nanoseconds
|
|
*/
|
|
#define FDB_AGEING_TIMEOUT_OFFSET 0x0014
|
|
|
|
/* Default VLAN tag for Host Port */
|
|
#define HOST_PORT_DF_VLAN_OFFSET 0x001C
|
|
|
|
/* Same as HOST_PORT_DF_VLAN_OFFSET */
|
|
#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET
|
|
|
|
/* Default VLAN tag for P1 Port */
|
|
#define P1_PORT_DF_VLAN_OFFSET 0x0020
|
|
|
|
/* Same as P1_PORT_DF_VLAN_OFFSET */
|
|
#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET
|
|
|
|
/* default VLAN tag for P2 Port */
|
|
#define P2_PORT_DF_VLAN_OFFSET 0x0024
|
|
|
|
/* Same as P2_PORT_DF_VLAN_OFFSET */
|
|
#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET
|
|
|
|
/* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */
|
|
#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100
|
|
|
|
/* VLAN-FID Table offset for EMAC */
|
|
#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define PORT_DESC0_HI 0x2104
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define PORT_DESC0_LO 0x2F6C
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define PORT_DESC1_HI 0x3DD4
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define PORT_DESC1_LO 0x4C3C
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define HOST_DESC0_HI 0x5AA4
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define HOST_DESC0_LO 0x5F0C
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define HOST_DESC1_HI 0x6374
|
|
|
|
/* Packet descriptor Q reserved memory */
|
|
#define HOST_DESC1_LO 0x67DC
|
|
|
|
/* Special packet descriptor Q reserved memory */
|
|
#define HOST_SPPD0 0x7AAC
|
|
|
|
/* Special acket descriptor Q reserved memory */
|
|
#define HOST_SPPD1 0x7EAC
|
|
|
|
/* IEP count cycle counter*/
|
|
#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC
|
|
|
|
/* IEP count hi roll over count */
|
|
#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4
|
|
|
|
/* IEP count hi sw counter */
|
|
#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8
|
|
|
|
/* Set clock descriptor */
|
|
#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC
|
|
|
|
/* IEP count syncout reduction factor */
|
|
#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C
|
|
|
|
/* IEP count syncout reduction counter */
|
|
#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440
|
|
|
|
/* IEP count syncout start time cycle counter */
|
|
#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444
|
|
|
|
/* Control variable to generate SYNC1 */
|
|
#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C
|
|
|
|
/* SystemTime Sync0 periodicity */
|
|
#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450
|
|
|
|
/* pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay */
|
|
#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454
|
|
|
|
/* pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay */
|
|
#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458
|
|
|
|
/* Set clock operation done signal for next task */
|
|
#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C
|
|
|
|
/* Set clock operation done signal for next task */
|
|
#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460
|
|
|
|
/* New list is copied at this time */
|
|
#define TAS_CONFIG_CHANGE_TIME 0x000C
|
|
|
|
/* config change error counter */
|
|
#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014
|
|
|
|
/* TAS List update pending flag */
|
|
#define TAS_CONFIG_PENDING 0x0018
|
|
|
|
/* TAS list update trigger flag */
|
|
#define TAS_CONFIG_CHANGE 0x0019
|
|
|
|
/* List length for new TAS schedule */
|
|
#define TAS_ADMIN_LIST_LENGTH 0x001A
|
|
|
|
/* Currently active TAS list index */
|
|
#define TAS_ACTIVE_LIST_INDEX 0x001B
|
|
|
|
/* Cycle time for the new TAS schedule */
|
|
#define TAS_ADMIN_CYCLE_TIME 0x001C
|
|
|
|
/* Cycle counts remaining till the TAS list update */
|
|
#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020
|
|
|
|
/* Base Flow ID for sending Packets to Host for Slice0 */
|
|
#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024
|
|
|
|
/* Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET */
|
|
#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET
|
|
|
|
/* Base Flow ID for sending mgmt and Tx TS to Host for Slice0 */
|
|
#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026
|
|
|
|
/* Same as PSI_L_MGMT_FLOW_ID_OFFSET */
|
|
#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET
|
|
|
|
/* Queue number for Special Packets written here */
|
|
#define SPL_PKT_DEFAULT_PRIORITY 0x0028
|
|
|
|
/* Express Preemptible Queue Mask */
|
|
#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029
|
|
|
|
/* Port1/Port2 Default Queue number for untagged Packets, only 1B is used */
|
|
#define QUEUE_NUM_UNTAGGED 0x002A
|
|
|
|
/* Stores the table used for priority regeneration. 1B per PCP/Queue */
|
|
#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C
|
|
|
|
/* For marking Packet as priority/express (this feature is disabled) or
|
|
* cut-through/S&F.
|
|
*/
|
|
#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034
|
|
|
|
/* Stores the table used for priority mapping. 1B per PCP/Queue */
|
|
#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C
|
|
|
|
/* Used to notify the FW of the current link speed */
|
|
#define PORT_LINK_SPEED_OFFSET 0x00A8
|
|
|
|
/* 2k memory pointer reserved for default writes by PRU0*/
|
|
#define DEFAULT_MSMC_Q_OFFSET 0x00AC
|
|
|
|
/* TAS gate mask for windows list0 */
|
|
#define TAS_GATE_MASK_LIST0 0x0100
|
|
|
|
/* TAS gate mask for windows list1 */
|
|
#define TAS_GATE_MASK_LIST1 0x0350
|
|
|
|
/* Memory to Enable/Disable Preemption on TX side */
|
|
#define PRE_EMPTION_ENABLE_TX 0x05A0
|
|
|
|
/* Active State of Preemption on TX side */
|
|
#define PRE_EMPTION_ACTIVE_TX 0x05A1
|
|
|
|
/* Memory to Enable/Disable Verify State Machine Preemption */
|
|
#define PRE_EMPTION_ENABLE_VERIFY 0x05A2
|
|
|
|
/* Verify Status of State Machine */
|
|
#define PRE_EMPTION_VERIFY_STATUS 0x05A3
|
|
|
|
/* Non Final Fragment Size supported by Link Partner */
|
|
#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4
|
|
|
|
/* Non Final Fragment Size supported by Firmware */
|
|
#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6
|
|
|
|
/* Time in ms the State machine waits for respond Packet */
|
|
#define PRE_EMPTION_VERIFY_TIME 0x05A8
|
|
|
|
/* Memory used for R30 related management commands */
|
|
#define MGR_R30_CMD_OFFSET 0x05AC
|
|
|
|
/* HW Buffer Pool0 base address */
|
|
#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC
|
|
|
|
/* 16B for Host Egress MSMC Q (Pre-emptible) context */
|
|
#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684
|
|
|
|
/* Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL' */
|
|
#define FDB_CMD_BUFFER 0x0894
|
|
|
|
/* TAS queue max sdu length list */
|
|
#define TAS_QUEUE_MAX_SDU_LIST 0x08FA
|
|
|
|
/* Used by FW to generate random number with the SEED value */
|
|
#define HD_RAND_SEED_OFFSET 0x0934
|
|
|
|
/* 16B for Host Egress MSMC Q (Express) context */
|
|
#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940
|
|
|
|
/* Start of 32 bits PA_STAT counters */
|
|
#define PA_STAT_32b_START_OFFSET 0x0080
|
|
|
|
#define FW_RTU_PKT_DROP 0x0088
|
|
#define FW_Q0_OVERFLOW 0x0090
|
|
#define FW_Q1_OVERFLOW 0x0098
|
|
#define FW_Q2_OVERFLOW 0x00A0
|
|
#define FW_Q3_OVERFLOW 0x00A8
|
|
#define FW_Q4_OVERFLOW 0x00B0
|
|
#define FW_Q5_OVERFLOW 0x00B8
|
|
#define FW_Q6_OVERFLOW 0x00C0
|
|
#define FW_Q7_OVERFLOW 0x00C8
|
|
#define FW_DROPPED_PKT 0x00F8
|
|
#define FW_RX_ERROR 0x0100
|
|
#define FW_RX_DS_INVALID 0x0108
|
|
#define FW_TX_DROPPED_PACKET 0x0110
|
|
#define FW_TX_TS_DROPPED_PACKET 0x0118
|
|
#define FW_INF_PORT_DISABLED 0x0120
|
|
#define FW_INF_SAV 0x0128
|
|
#define FW_INF_SA_DL 0x0130
|
|
#define FW_INF_PORT_BLOCKED 0x0138
|
|
#define FW_INF_DROP_TAGGED 0x0140
|
|
#define FW_INF_DROP_PRIOTAGGED 0x0148
|
|
#define FW_INF_DROP_NOTAG 0x0150
|
|
#define FW_INF_DROP_NOTMEMBER 0x0158
|
|
#define FW_RX_EOF_SHORT_FRMERR 0x0188
|
|
#define FW_RX_B0_DROP_EARLY_EOF 0x0190
|
|
#define FW_TX_JUMBO_FRM_CUTOFF 0x0198
|
|
#define FW_RX_EXP_FRAG_Q_DROP 0x01A0
|
|
#define FW_RX_FIFO_OVERRUN 0x01A8
|
|
#define FW_CUT_THR_PKT 0x01B0
|
|
#define FW_HOST_RX_PKT_CNT 0x0248
|
|
#define FW_HOST_TX_PKT_CNT 0x0250
|
|
#define FW_HOST_EGRESS_Q_PRE_OVERFLOW 0x0258
|
|
#define FW_HOST_EGRESS_Q_EXP_OVERFLOW 0x0260
|
|
|
|
#endif /* __NET_TI_ICSSG_SWITCH_MAP_H */
|