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d3836052fe
TGL platforms support either SGMII or 2500BASE-X, which is determined by reading a SERDES register. Thus, plat->phy_interface (and phylink's supported_interfaces) depend on this. Use the new .get_interfaces() method to set both plat->phy_interface and the supported_interfaces bitmap. This removes the only user of the .speed_mode_2500() method. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/E1uASLx-0021Qs-Uz@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020, Intel Corporation
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* DWMAC Intel header file
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*/
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#ifndef __DWMAC_INTEL_H__
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#define __DWMAC_INTEL_H__
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#define POLL_DELAY_US 8
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/* SERDES Register */
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#define SERDES_GCR 0x0 /* Global Conguration */
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#define SERDES_GSR0 0x5 /* Global Status Reg0 */
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#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
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/* SERDES defines */
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#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
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#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
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#define SERDES_RST BIT(2) /* Serdes Reset */
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#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
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#define SERDES_RATE_MASK GENMASK(9, 8)
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#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
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#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
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#define SERDES_PWR_ST_SHIFT 4
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#define SERDES_PWR_ST_P0 0x0
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#define SERDES_PWR_ST_P3 0x3
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#define SERDES_LINK_MODE_2G5 0x3
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#define SERSED_LINK_MODE_1G 0x2
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#define SERDES_PCLK_37p5MHZ 0x0
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#define SERDES_PCLK_70MHZ 0x1
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#define SERDES_RATE_PCIE_GEN1 0x0
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#define SERDES_RATE_PCIE_GEN2 0x1
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#define SERDES_RATE_PCIE_SHIFT 8
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#define SERDES_PCLK_SHIFT 12
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#define INTEL_MGBE_ADHOC_ADDR 0x15
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#define INTEL_MGBE_XPCS_ADDR 0x16
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/* Cross-timestamping defines */
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#define ART_CPUID_LEAF 0x15
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#define EHL_PSE_ART_MHZ 19200000
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/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
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#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3)
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#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
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#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3)
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#define PSE_PTP_CLK_FREQ_256MHZ (0)
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#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0)
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#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
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#define PCH_PTP_CLK_FREQ_200MHZ (0)
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/* Modphy Register index */
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#define R_PCH_FIA_15_PCR_LOS1_REG_BASE 8
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#define R_PCH_FIA_15_PCR_LOS2_REG_BASE 9
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#define R_PCH_FIA_15_PCR_LOS3_REG_BASE 10
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#define R_PCH_FIA_15_PCR_LOS4_REG_BASE 11
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#define R_PCH_FIA_15_PCR_LOS5_REG_BASE 12
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#define B_PCH_FIA_PCR_L0O GENMASK(3, 0)
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#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0 13
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#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2 14
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#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7 15
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#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10 16
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#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30 17
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#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0 18
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#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2 19
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#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7 20
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#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10 21
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#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30 22
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#define B_MODPHY_PCR_LCPLL_DWORD0_1G 0x46AAAA41
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#define N_MODPHY_PCR_LCPLL_DWORD2_1G 0x00000139
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#define N_MODPHY_PCR_LCPLL_DWORD7_1G 0x002A0003
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#define N_MODPHY_PCR_LPPLL_DWORD10_1G 0x00170008
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#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G 0x0000D4AC
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#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G 0x58555551
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#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G 0x0000012D
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#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G 0x001F0003
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#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G 0x00170008
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#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G 0x8200ACAC
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#endif /* __DWMAC_INTEL_H__ */
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