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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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70f8986ece
This patch implements the CN20k MBOX communication between PF and it's VFs. CN20K silicon got extra interrupt of MBOX response for trigger interrupt. Also few of the CSR offsets got changed in CN20K against prior series of silicons. Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Link: https://patch.msgid.link/1749639716-13868-7-git-send-email-sbhatta@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
252 lines
6.6 KiB
C
252 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Ethernet driver
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*
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* Copyright (C) 2024 Marvell.
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*
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*/
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#include "otx2_common.h"
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#include "otx2_reg.h"
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#include "otx2_struct.h"
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#include "cn10k.h"
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static struct dev_hw_ops cn20k_hw_ops = {
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.pfaf_mbox_intr_handler = cn20k_pfaf_mbox_intr_handler,
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.vfaf_mbox_intr_handler = cn20k_vfaf_mbox_intr_handler,
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.pfvf_mbox_intr_handler = cn20k_pfvf_mbox_intr_handler,
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};
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void cn20k_init(struct otx2_nic *pfvf)
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{
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pfvf->hw_ops = &cn20k_hw_ops;
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}
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EXPORT_SYMBOL(cn20k_init);
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/* CN20K mbox AF => PFx irq handler */
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irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq)
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{
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struct otx2_nic *pf = pf_irq;
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struct mbox *mw = &pf->mbox;
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struct otx2_mbox_dev *mdev;
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struct otx2_mbox *mbox;
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struct mbox_hdr *hdr;
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u64 pf_trig_val;
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pf_trig_val = otx2_read64(pf, RVU_PF_INT) & 0x3ULL;
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/* Clear the IRQ */
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otx2_write64(pf, RVU_PF_INT, pf_trig_val);
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if (pf_trig_val & BIT_ULL(0)) {
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mbox = &mw->mbox_up;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs)
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queue_work(pf->mbox_wq, &mw->mbox_up_wrk);
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trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF",
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BIT_ULL(0));
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}
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if (pf_trig_val & BIT_ULL(1)) {
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mbox = &mw->mbox;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs)
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queue_work(pf->mbox_wq, &mw->mbox_wrk);
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trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF",
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BIT_ULL(1));
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}
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return IRQ_HANDLED;
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}
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irqreturn_t cn20k_vfaf_mbox_intr_handler(int irq, void *vf_irq)
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{
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struct otx2_nic *vf = vf_irq;
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struct otx2_mbox_dev *mdev;
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struct otx2_mbox *mbox;
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struct mbox_hdr *hdr;
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u64 vf_trig_val;
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vf_trig_val = otx2_read64(vf, RVU_VF_INT) & 0x3ULL;
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/* Clear the IRQ */
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otx2_write64(vf, RVU_VF_INT, vf_trig_val);
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/* Read latest mbox data */
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smp_rmb();
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if (vf_trig_val & BIT_ULL(1)) {
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/* Check for PF => VF response messages */
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mbox = &vf->mbox.mbox;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs)
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queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk);
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trace_otx2_msg_interrupt(mbox->pdev, "DOWN reply from PF0 to VF",
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BIT_ULL(1));
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}
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if (vf_trig_val & BIT_ULL(0)) {
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/* Check for PF => VF notification messages */
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mbox = &vf->mbox.mbox_up;
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mdev = &mbox->dev[0];
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otx2_sync_mbox_bbuf(mbox, 0);
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hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);
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if (hdr->num_msgs)
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queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk);
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trace_otx2_msg_interrupt(mbox->pdev, "UP message from PF0 to VF",
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BIT_ULL(0));
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}
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return IRQ_HANDLED;
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}
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void cn20k_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
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{
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/* Clear PF <=> VF mailbox IRQ */
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull);
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/* Enable PF <=> VF mailbox IRQ */
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(0), INTR_MASK(numvfs));
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(0), INTR_MASK(numvfs));
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if (numvfs > 64) {
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numvfs -= 64;
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1SX(1),
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INTR_MASK(numvfs));
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1SX(1),
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INTR_MASK(numvfs));
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}
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}
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void cn20k_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
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{
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int vector, intr_vec, vec = 0;
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/* Disable PF <=> VF mailbox IRQ */
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(0), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INT_ENA_W1CX(1), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(0), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INT_ENA_W1CX(1), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(0), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(0), ~0ull);
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if (numvfs > 64) {
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otx2_write64(pf, RVU_MBOX_PF_VFPF_INTX(1), ~0ull);
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otx2_write64(pf, RVU_MBOX_PF_VFPF1_INTX(1), ~0ull);
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}
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for (intr_vec = RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=
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RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) {
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vector = pci_irq_vector(pf->pdev, intr_vec);
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free_irq(vector, pf->hw.pfvf_irq_devid[vec]);
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}
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}
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irqreturn_t cn20k_pfvf_mbox_intr_handler(int irq, void *pf_irq)
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{
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struct pf_irq_data *irq_data = pf_irq;
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struct otx2_nic *pf = irq_data->pf;
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struct mbox *mbox;
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u64 intr;
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/* Sync with mbox memory region */
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rmb();
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/* Clear interrupts */
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intr = otx2_read64(pf, irq_data->intr_status);
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otx2_write64(pf, irq_data->intr_status, intr);
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mbox = pf->mbox_pfvf;
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if (intr)
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trace_otx2_msg_interrupt(pf->pdev, "VF(s) to PF", intr);
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irq_data->pf_queue_work_hdlr(mbox, pf->mbox_pfvf_wq, irq_data->start,
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irq_data->mdevs, intr);
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return IRQ_HANDLED;
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}
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int cn20k_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs)
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{
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struct otx2_hw *hw = &pf->hw;
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struct pf_irq_data *irq_data;
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int intr_vec, ret, vec = 0;
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char *irq_name;
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/* irq data for 4 PF intr vectors */
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irq_data = devm_kcalloc(pf->dev, 4,
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sizeof(struct pf_irq_data), GFP_KERNEL);
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if (!irq_data)
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return -ENOMEM;
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for (intr_vec = RVU_MBOX_PF_INT_VEC_VFPF_MBOX0; intr_vec <=
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RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1; intr_vec++, vec++) {
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switch (intr_vec) {
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case RVU_MBOX_PF_INT_VEC_VFPF_MBOX0:
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irq_data[vec].intr_status =
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RVU_MBOX_PF_VFPF_INTX(0);
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irq_data[vec].start = 0;
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irq_data[vec].mdevs = 64;
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break;
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case RVU_MBOX_PF_INT_VEC_VFPF_MBOX1:
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irq_data[vec].intr_status =
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RVU_MBOX_PF_VFPF_INTX(1);
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irq_data[vec].start = 64;
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irq_data[vec].mdevs = 96;
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break;
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case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0:
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irq_data[vec].intr_status =
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RVU_MBOX_PF_VFPF1_INTX(0);
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irq_data[vec].start = 0;
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irq_data[vec].mdevs = 64;
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break;
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case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1:
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irq_data[vec].intr_status =
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RVU_MBOX_PF_VFPF1_INTX(1);
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irq_data[vec].start = 64;
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irq_data[vec].mdevs = 96;
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break;
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}
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irq_data[vec].pf_queue_work_hdlr = otx2_queue_vf_work;
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irq_data[vec].vec_num = intr_vec;
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irq_data[vec].pf = pf;
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/* Register mailbox interrupt handler */
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irq_name = &hw->irq_name[intr_vec * NAME_SIZE];
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if (pf->pcifunc)
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snprintf(irq_name, NAME_SIZE,
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"RVUPF%d_VF%d Mbox%d", rvu_get_pf(pf->pdev,
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pf->pcifunc), vec / 2, vec % 2);
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else
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snprintf(irq_name, NAME_SIZE, "RVUPF_VF%d Mbox%d",
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vec / 2, vec % 2);
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hw->pfvf_irq_devid[vec] = &irq_data[vec];
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ret = request_irq(pci_irq_vector(pf->pdev, intr_vec),
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pf->hw_ops->pfvf_mbox_intr_handler, 0,
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irq_name,
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&irq_data[vec]);
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if (ret) {
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dev_err(pf->dev,
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"RVUPF: IRQ registration failed for PFVF mbox0 irq\n");
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return ret;
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}
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}
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cn20k_enable_pfvf_mbox_intr(pf, numvfs);
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return 0;
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}
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