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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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25d51ebf0f
Number of RVU PFs on CN20K silicon have increased to 96 from maximum of 32 that were supported on earlier silicons. Every RVU PF and VF is identified by HW using a 16bit PF_FUNC value. Due to the change in Max number of PFs in CN20K, the bit encoding of this PF_FUNC has changed. This patch handles the change by using helper functions(using silicon check) to use PF,VF masks and shifts to support both new silicon CN20K, OcteonTx series. These helper functions are used in different modules. Also moved the NIX AF register offset macros to other files which will be posted in coming patches. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Link: https://patch.msgid.link/1749639716-13868-2-git-send-email-sbhatta@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
123 lines
2.6 KiB
C
123 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Admin Function driver
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*
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* Copyright (C) 2021 Marvell.
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*
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*/
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#include <linux/pci.h>
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#include "rvu.h"
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/* SDP PF device id */
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#define PCI_DEVID_OTX2_SDP_PF 0xA0F6
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/* Maximum SDP blocks in a chip */
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#define MAX_SDP 2
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/* SDP PF number */
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static int sdp_pf_num[MAX_SDP] = {-1, -1};
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bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc)
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{
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u16 pf = rvu_get_pf(rvu->pdev, pcifunc);
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u32 found = 0, i = 0;
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while (i < MAX_SDP) {
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if (pf == sdp_pf_num[i])
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found = 1;
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i++;
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}
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if (!found)
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return false;
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return true;
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}
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bool is_sdp_pf(struct rvu *rvu, u16 pcifunc)
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{
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return (is_sdp_pfvf(rvu, pcifunc) &&
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!(pcifunc & RVU_PFVF_FUNC_MASK));
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}
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#define RVU_SDP_VF_DEVID 0xA0F7
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bool is_sdp_vf(struct rvu *rvu, u16 pcifunc)
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{
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if (!(pcifunc & ~RVU_PFVF_FUNC_MASK))
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return (rvu->vf_devid == RVU_SDP_VF_DEVID);
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return (is_sdp_pfvf(rvu, pcifunc) &&
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!!(pcifunc & RVU_PFVF_FUNC_MASK));
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}
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int rvu_sdp_init(struct rvu *rvu)
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{
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struct pci_dev *pdev = NULL;
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struct rvu_pfvf *pfvf;
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u32 i = 0;
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if (rvu->fwdata->channel_data.valid) {
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sdp_pf_num[0] = 0;
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pfvf = &rvu->pf[sdp_pf_num[0]];
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pfvf->sdp_info = &rvu->fwdata->channel_data.info;
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return 0;
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}
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while ((i < MAX_SDP) && (pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVID_OTX2_SDP_PF,
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pdev)) != NULL) {
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/* The RVU PF number is one less than bus number */
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sdp_pf_num[i] = pdev->bus->number - 1;
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pfvf = &rvu->pf[sdp_pf_num[i]];
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pfvf->sdp_info = devm_kzalloc(rvu->dev,
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sizeof(struct sdp_node_info),
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GFP_KERNEL);
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if (!pfvf->sdp_info) {
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pci_dev_put(pdev);
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return -ENOMEM;
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}
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dev_info(rvu->dev, "SDP PF number:%d\n", sdp_pf_num[i]);
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i++;
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}
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pci_dev_put(pdev);
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return 0;
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}
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int
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rvu_mbox_handler_set_sdp_chan_info(struct rvu *rvu,
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struct sdp_chan_info_msg *req,
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struct msg_rsp *rsp)
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{
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struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
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memcpy(pfvf->sdp_info, &req->info, sizeof(struct sdp_node_info));
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dev_info(rvu->dev, "AF: SDP%d max_vfs %d num_pf_rings %d pf_srn %d\n",
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req->info.node_id, req->info.max_vfs, req->info.num_pf_rings,
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req->info.pf_srn);
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return 0;
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}
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int
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rvu_mbox_handler_get_sdp_chan_info(struct rvu *rvu, struct msg_req *req,
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struct sdp_get_chan_info_msg *rsp)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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int blkaddr;
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if (!hw->cap.programmable_chans) {
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rsp->chan_base = NIX_CHAN_SDP_CH_START;
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rsp->num_chan = NIX_CHAN_SDP_NUM_CHANS;
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} else {
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
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rsp->chan_base = hw->sdp_chan_base;
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rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL;
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}
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return 0;
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}
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