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370c2374bf
This implementation uses separate trigger interrupts for request, response messages against using trigger message data in CN10K. This patch adds support for basic mbox implementation for CN20K from NIC PF side. Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Link: https://patch.msgid.link/1749639716-13868-5-git-send-email-sbhatta@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell RVU Admin Function driver
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*
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* Copyright (C) 2024 Marvell.
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*
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*/
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#ifndef STRUCT_H
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#define STRUCT_H
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/*
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* CN20k RVU PF MBOX Interrupt Vector Enumeration
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*
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* Vectors 0 - 3 are compatible with pre cn20k and hence
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* existing macros are being reused.
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*/
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enum rvu_mbox_pf_int_vec_e {
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RVU_MBOX_PF_INT_VEC_VFPF_MBOX0 = 0x4,
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RVU_MBOX_PF_INT_VEC_VFPF_MBOX1 = 0x5,
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RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0 = 0x6,
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RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1 = 0x7,
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RVU_MBOX_PF_INT_VEC_AFPF_MBOX = 0x8,
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RVU_MBOX_PF_INT_VEC_CNT = 0x9,
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};
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/* RVU Admin function Interrupt Vector Enumeration */
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enum rvu_af_cn20k_int_vec_e {
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RVU_AF_CN20K_INT_VEC_POISON = 0x0,
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RVU_AF_CN20K_INT_VEC_PFFLR0 = 0x1,
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RVU_AF_CN20K_INT_VEC_PFFLR1 = 0x2,
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RVU_AF_CN20K_INT_VEC_PFME0 = 0x3,
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RVU_AF_CN20K_INT_VEC_PFME1 = 0x4,
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RVU_AF_CN20K_INT_VEC_GEN = 0x5,
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RVU_AF_CN20K_INT_VEC_PFAF_MBOX0 = 0x6,
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RVU_AF_CN20K_INT_VEC_PFAF_MBOX1 = 0x7,
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RVU_AF_CN20K_INT_VEC_PFAF1_MBOX0 = 0x8,
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RVU_AF_CN20K_INT_VEC_PFAF1_MBOX1 = 0x9,
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RVU_AF_CN20K_INT_VEC_CNT = 0xa,
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};
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#endif
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