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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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17fcb3dc12
This is [1/3] part of hinic3 Ethernet driver initial submission. With this patch hinic3 is a valid kernel module but non-functional driver. The driver parts contained in this patch: Module initialization. PCI driver registration but with empty id_table. Auxiliary driver registration. Net device_ops registration but open/stop are empty stubs. tx/rx logic. All major data structures of the driver are fully introduced with the code that uses them but without their initialization code that requires management interface with the hw. Co-developed-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Co-developed-by: Gur Stavi <gur.stavi@huawei.com> Signed-off-by: Gur Stavi <gur.stavi@huawei.com> Link: https://patch.msgid.link/76a137ffdfe115c737c2c224f0c93b60ba53cc16.1747736586.git.gur.stavi@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_MGMT_INTERFACE_H_
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#define _HINIC3_MGMT_INTERFACE_H_
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/if_ether.h>
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#include "hinic3_hw_intf.h"
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struct l2nic_cmd_feature_nego {
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struct mgmt_msg_head msg_head;
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u16 func_id;
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u8 opcode;
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u8 rsvd;
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u64 s_feature[4];
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};
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enum l2nic_func_tbl_cfg_bitmap {
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L2NIC_FUNC_TBL_CFG_INIT = 0,
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L2NIC_FUNC_TBL_CFG_RX_BUF_SIZE = 1,
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L2NIC_FUNC_TBL_CFG_MTU = 2,
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};
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struct l2nic_func_tbl_cfg {
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u16 rx_wqe_buf_size;
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u16 mtu;
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u32 rsvd[9];
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};
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struct l2nic_cmd_set_func_tbl {
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struct mgmt_msg_head msg_head;
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u16 func_id;
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u16 rsvd;
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u32 cfg_bitmap;
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struct l2nic_func_tbl_cfg tbl_cfg;
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};
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struct l2nic_cmd_set_mac {
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struct mgmt_msg_head msg_head;
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u16 func_id;
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u16 vlan_id;
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u16 rsvd1;
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u8 mac[ETH_ALEN];
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};
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struct l2nic_cmd_update_mac {
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struct mgmt_msg_head msg_head;
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u16 func_id;
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u16 vlan_id;
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u16 rsvd1;
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u8 old_mac[ETH_ALEN];
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u16 rsvd2;
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u8 new_mac[ETH_ALEN];
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};
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struct l2nic_cmd_force_pkt_drop {
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struct mgmt_msg_head msg_head;
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u8 port;
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u8 rsvd1[3];
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};
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/* Commands between NIC to fw */
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enum l2nic_cmd {
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/* FUNC CFG */
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L2NIC_CMD_SET_FUNC_TBL = 5,
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L2NIC_CMD_SET_VPORT_ENABLE = 6,
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L2NIC_CMD_SET_SQ_CI_ATTR = 8,
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L2NIC_CMD_CLEAR_QP_RESOURCE = 11,
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L2NIC_CMD_FEATURE_NEGO = 15,
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L2NIC_CMD_SET_MAC = 21,
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L2NIC_CMD_DEL_MAC = 22,
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L2NIC_CMD_UPDATE_MAC = 23,
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L2NIC_CMD_CFG_RSS = 60,
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L2NIC_CMD_CFG_RSS_HASH_KEY = 63,
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L2NIC_CMD_CFG_RSS_HASH_ENGINE = 64,
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L2NIC_CMD_SET_RSS_CTX_TBL = 65,
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L2NIC_CMD_QOS_DCB_STATE = 110,
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L2NIC_CMD_FORCE_PKT_DROP = 113,
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L2NIC_CMD_MAX = 256,
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};
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enum hinic3_nic_feature_cap {
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HINIC3_NIC_F_CSUM = BIT(0),
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HINIC3_NIC_F_SCTP_CRC = BIT(1),
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HINIC3_NIC_F_TSO = BIT(2),
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HINIC3_NIC_F_LRO = BIT(3),
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HINIC3_NIC_F_UFO = BIT(4),
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HINIC3_NIC_F_RSS = BIT(5),
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HINIC3_NIC_F_RX_VLAN_FILTER = BIT(6),
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HINIC3_NIC_F_RX_VLAN_STRIP = BIT(7),
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HINIC3_NIC_F_TX_VLAN_INSERT = BIT(8),
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HINIC3_NIC_F_VXLAN_OFFLOAD = BIT(9),
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HINIC3_NIC_F_FDIR = BIT(11),
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HINIC3_NIC_F_PROMISC = BIT(12),
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HINIC3_NIC_F_ALLMULTI = BIT(13),
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HINIC3_NIC_F_RATE_LIMIT = BIT(16),
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};
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#define HINIC3_NIC_F_ALL_MASK 0x33bff
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#define HINIC3_NIC_DRV_DEFAULT_FEATURE 0x3f03f
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#endif
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