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df9fd2a3ce
Enables reading the max rq and wq entries supported from the hw. Enables 16k rq and wq entries on hw that supports. Co-developed-by: Nelson Escobar <neescoba@cisco.com> Signed-off-by: Nelson Escobar <neescoba@cisco.com> Co-developed-by: John Daley <johndale@cisco.com> Signed-off-by: John Daley <johndale@cisco.com> Signed-off-by: Satish Kharat <satishkh@cisco.com> Link: https://patch.msgid.link/20250304-enic_cleanup_and_ext_cq-v2-8-85804263dad8@cisco.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _VNIC_ENIC_H_
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#define _VNIC_ENIC_H_
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/* Device-specific region: enet configuration */
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struct vnic_enet_config {
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u32 flags;
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u32 wq_desc_count;
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u32 rq_desc_count;
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u16 mtu;
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u16 intr_timer_deprecated;
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u8 intr_timer_type;
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u8 intr_mode;
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char devname[16];
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u32 intr_timer_usec;
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u16 loop_tag;
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u16 vf_rq_count;
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u16 num_arfs;
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u8 reserved[66];
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u32 max_rq_ring; // MAX RQ ring size
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u32 max_wq_ring; // MAX WQ ring size
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u32 max_cq_ring; // MAX CQ ring size
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u32 rdma_rsvd_lkey; // Reserved (privileged) LKey
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};
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#define VENETF_TSO 0x1 /* TSO enabled */
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#define VENETF_LRO 0x2 /* LRO enabled */
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#define VENETF_RXCSUM 0x4 /* RX csum enabled */
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#define VENETF_TXCSUM 0x8 /* TX csum enabled */
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#define VENETF_RSS 0x10 /* RSS enabled */
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#define VENETF_RSSHASH_IPV4 0x20 /* Hash on IPv4 fields */
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#define VENETF_RSSHASH_TCPIPV4 0x40 /* Hash on TCP + IPv4 fields */
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#define VENETF_RSSHASH_IPV6 0x80 /* Hash on IPv6 fields */
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#define VENETF_RSSHASH_TCPIPV6 0x100 /* Hash on TCP + IPv6 fields */
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#define VENETF_RSSHASH_IPV6_EX 0x200 /* Hash on IPv6 extended fields */
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#define VENETF_RSSHASH_TCPIPV6_EX 0x400 /* Hash on TCP + IPv6 ext. fields */
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#define VENETF_LOOP 0x800 /* Loopback enabled */
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#define VENETF_VXLAN 0x10000 /* VxLAN offload */
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#define VENET_INTR_TYPE_MIN 0 /* Timer specs min interrupt spacing */
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#define VENET_INTR_TYPE_IDLE 1 /* Timer specs idle time before irq */
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#define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */
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#define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */
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#define VENET_INTR_MODE_INTX 2 /* Try INTx only */
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#endif /* _VNIC_ENIC_H_ */
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