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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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df9fd2a3ce
Enables reading the max rq and wq entries supported from the hw. Enables 16k rq and wq entries on hw that supports. Co-developed-by: Nelson Escobar <neescoba@cisco.com> Signed-off-by: Nelson Escobar <neescoba@cisco.com> Co-developed-by: John Daley <johndale@cisco.com> Signed-off-by: John Daley <johndale@cisco.com> Signed-off-by: Satish Kharat <satishkh@cisco.com> Link: https://patch.msgid.link/20250304-enic_cleanup_and_ext_cq-v2-8-85804263dad8@cisco.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
117 lines
3.2 KiB
C
117 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright 2025 Cisco Systems, Inc. All rights reserved.
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#include <net/netdev_queues.h>
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#include "enic_res.h"
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#include "enic.h"
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#include "enic_wq.h"
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#define ENET_CQ_DESC_COMP_NDX_BITS 14
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#define ENET_CQ_DESC_COMP_NDX_MASK GENMASK(ENET_CQ_DESC_COMP_NDX_BITS - 1, 0)
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static void enic_wq_cq_desc_dec(const struct cq_desc *desc_arg, bool ext_wq,
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u8 *type, u8 *color, u16 *q_number,
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u16 *completed_index)
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{
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const struct cq_desc *desc = desc_arg;
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const u8 type_color = desc->type_color;
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*color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;
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/*
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* Make sure color bit is read from desc *before* other fields
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* are read from desc. Hardware guarantees color bit is last
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* bit (byte) written. Adding the rmb() prevents the compiler
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* and/or CPU from reordering the reads which would potentially
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* result in reading stale values.
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*/
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rmb();
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*type = type_color & CQ_DESC_TYPE_MASK;
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*q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;
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if (ext_wq)
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*completed_index = le16_to_cpu(desc->completed_index) &
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ENET_CQ_DESC_COMP_NDX_MASK;
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else
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*completed_index = le16_to_cpu(desc->completed_index) &
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CQ_DESC_COMP_NDX_MASK;
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}
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void enic_free_wq_buf(struct vnic_wq *wq, struct vnic_wq_buf *buf)
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{
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struct enic *enic = vnic_dev_priv(wq->vdev);
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if (buf->sop)
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dma_unmap_single(&enic->pdev->dev, buf->dma_addr, buf->len,
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DMA_TO_DEVICE);
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else
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dma_unmap_page(&enic->pdev->dev, buf->dma_addr, buf->len,
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DMA_TO_DEVICE);
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if (buf->os_buf)
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dev_kfree_skb_any(buf->os_buf);
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}
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static void enic_wq_free_buf(struct vnic_wq *wq, struct cq_desc *cq_desc,
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struct vnic_wq_buf *buf, void *opaque)
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{
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struct enic *enic = vnic_dev_priv(wq->vdev);
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enic->wq[wq->index].stats.cq_work++;
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enic->wq[wq->index].stats.cq_bytes += buf->len;
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enic_free_wq_buf(wq, buf);
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}
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static void enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,
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u8 type, u16 q_number, u16 completed_index)
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{
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struct enic *enic = vnic_dev_priv(vdev);
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spin_lock(&enic->wq[q_number].lock);
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vnic_wq_service(&enic->wq[q_number].vwq, cq_desc,
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completed_index, enic_wq_free_buf, NULL);
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if (netif_tx_queue_stopped(netdev_get_tx_queue(enic->netdev, q_number))
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&& vnic_wq_desc_avail(&enic->wq[q_number].vwq) >=
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(MAX_SKB_FRAGS + ENIC_DESC_MAX_SPLITS)) {
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netif_wake_subqueue(enic->netdev, q_number);
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enic->wq[q_number].stats.wake++;
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}
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spin_unlock(&enic->wq[q_number].lock);
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}
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unsigned int enic_wq_cq_service(struct enic *enic, unsigned int cq_index,
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unsigned int work_to_do)
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{
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struct vnic_cq *cq = &enic->cq[cq_index];
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u16 q_number, completed_index;
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unsigned int work_done = 0;
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struct cq_desc *cq_desc;
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u8 type, color;
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bool ext_wq;
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ext_wq = cq->ring.size > ENIC_MAX_WQ_DESCS_DEFAULT;
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cq_desc = (struct cq_desc *)vnic_cq_to_clean(cq);
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enic_wq_cq_desc_dec(cq_desc, ext_wq, &type, &color,
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&q_number, &completed_index);
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while (color != cq->last_color) {
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enic_wq_service(cq->vdev, cq_desc, type, q_number,
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completed_index);
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vnic_cq_inc_to_clean(cq);
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if (++work_done >= work_to_do)
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break;
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cq_desc = (struct cq_desc *)vnic_cq_to_clean(cq);
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enic_wq_cq_desc_dec(cq_desc, ext_wq, &type, &color,
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&q_number, &completed_index);
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}
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return work_done;
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}
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