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29c5b358f3
Backing store or context memory on the host helps the device to manage rings, stats and other resources. Context memory is allocated with the help of ring alloc/free functions. Signed-off-by: Vikas Gupta <vikas.gupta@broadcom.com> Reviewed-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com> Reviewed-by: Rajashekar Hudumula <rajashekar.hudumula@broadcom.com> Link: https://patch.msgid.link/20250701143511.280702-7-vikas.gupta@broadcom.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
188 lines
5.1 KiB
C
188 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2025 Broadcom */
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#ifndef _BNGE_RMEM_H_
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#define _BNGE_RMEM_H_
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struct bnge_ctx_mem_type;
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struct bnge_dev;
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#define PTU_PTE_VALID 0x1UL
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#define PTU_PTE_LAST 0x2UL
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#define PTU_PTE_NEXT_TO_LAST 0x4UL
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struct bnge_ring_mem_info {
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/* Number of pages to next level */
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int nr_pages;
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int page_size;
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u16 flags;
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#define BNGE_RMEM_VALID_PTE_FLAG 1
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#define BNGE_RMEM_RING_PTE_FLAG 2
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#define BNGE_RMEM_USE_FULL_PAGE_FLAG 4
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u16 depth;
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void **pg_arr;
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dma_addr_t *dma_arr;
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__le64 *pg_tbl;
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dma_addr_t dma_pg_tbl;
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int vmem_size;
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void **vmem;
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struct bnge_ctx_mem_type *ctx_mem;
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};
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/* The hardware supports certain page sizes.
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* Use the supported page sizes to allocate the rings.
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*/
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#if (PAGE_SHIFT < 12)
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#define BNGE_PAGE_SHIFT 12
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#elif (PAGE_SHIFT <= 13)
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#define BNGE_PAGE_SHIFT PAGE_SHIFT
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#elif (PAGE_SHIFT < 16)
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#define BNGE_PAGE_SHIFT 13
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#else
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#define BNGE_PAGE_SHIFT 16
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#endif
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#define BNGE_PAGE_SIZE (1 << BNGE_PAGE_SHIFT)
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/* The RXBD length is 16-bit so we can only support page sizes < 64K */
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#if (PAGE_SHIFT > 15)
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#define BNGE_RX_PAGE_SHIFT 15
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#else
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#define BNGE_RX_PAGE_SHIFT PAGE_SHIFT
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#endif
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#define MAX_CTX_PAGES (BNGE_PAGE_SIZE / 8)
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#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
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struct bnge_ctx_pg_info {
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u32 entries;
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u32 nr_pages;
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void *ctx_pg_arr[MAX_CTX_PAGES];
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dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
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struct bnge_ring_mem_info ring_mem;
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struct bnge_ctx_pg_info **ctx_pg_tbl;
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};
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#define BNGE_MAX_TQM_SP_RINGS 1
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#define BNGE_MAX_TQM_FP_RINGS 8
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#define BNGE_MAX_TQM_RINGS \
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(BNGE_MAX_TQM_SP_RINGS + BNGE_MAX_TQM_FP_RINGS)
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#define BNGE_BACKING_STORE_CFG_LEGACY_LEN 256
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#define BNGE_SET_CTX_PAGE_ATTR(attr) \
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do { \
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if (BNGE_PAGE_SIZE == 0x2000) \
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attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \
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else if (BNGE_PAGE_SIZE == 0x10000) \
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attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \
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else \
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attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \
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} while (0)
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#define BNGE_CTX_MRAV_AV_SPLIT_ENTRY 0
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#define BNGE_CTX_QP \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP
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#define BNGE_CTX_SRQ \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ
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#define BNGE_CTX_CQ \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ
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#define BNGE_CTX_VNIC \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC
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#define BNGE_CTX_STAT \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT
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#define BNGE_CTX_STQM \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING
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#define BNGE_CTX_FTQM \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING
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#define BNGE_CTX_MRAV \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV
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#define BNGE_CTX_TIM \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM
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#define BNGE_CTX_TCK \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK
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#define BNGE_CTX_RCK \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK
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#define BNGE_CTX_MTQM \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING
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#define BNGE_CTX_SQDBS \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW
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#define BNGE_CTX_RQDBS \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW
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#define BNGE_CTX_SRQDBS \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW
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#define BNGE_CTX_CQDBS \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW
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#define BNGE_CTX_SRT_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE
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#define BNGE_CTX_SRT2_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE
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#define BNGE_CTX_CRT_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE
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#define BNGE_CTX_CRT2_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE
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#define BNGE_CTX_RIGP0_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE
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#define BNGE_CTX_L2_HWRM_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE
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#define BNGE_CTX_ROCE_HWRM_TRACE \
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FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE
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#define BNGE_CTX_MAX (BNGE_CTX_TIM + 1)
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#define BNGE_CTX_L2_MAX (BNGE_CTX_FTQM + 1)
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#define BNGE_CTX_INV ((u16)-1)
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#define BNGE_CTX_V2_MAX \
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(FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE + 1)
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#define BNGE_BS_CFG_ALL_DONE \
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FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE
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struct bnge_ctx_mem_type {
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u16 type;
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u16 entry_size;
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u32 flags;
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#define BNGE_CTX_MEM_TYPE_VALID \
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FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID
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u32 instance_bmap;
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u8 init_value;
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u8 entry_multiple;
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u16 init_offset;
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#define BNGE_CTX_INIT_INVALID_OFFSET 0xffff
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u32 max_entries;
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u32 min_entries;
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u8 last:1;
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u8 split_entry_cnt;
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#define BNGE_MAX_SPLIT_ENTRY 4
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union {
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struct {
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u32 qp_l2_entries;
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u32 qp_qp1_entries;
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u32 qp_fast_qpmd_entries;
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};
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u32 srq_l2_entries;
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u32 cq_l2_entries;
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u32 vnic_entries;
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struct {
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u32 mrav_av_entries;
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u32 mrav_num_entries_units;
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};
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u32 split[BNGE_MAX_SPLIT_ENTRY];
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};
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struct bnge_ctx_pg_info *pg_info;
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};
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struct bnge_ctx_mem_info {
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u8 tqm_fp_rings_count;
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u32 flags;
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#define BNGE_CTX_FLAG_INITED 0x01
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struct bnge_ctx_mem_type ctx_arr[BNGE_CTX_V2_MAX];
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};
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int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem);
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void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem);
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int bnge_alloc_ctx_mem(struct bnge_dev *bd);
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void bnge_free_ctx_mem(struct bnge_dev *bd);
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#endif /* _BNGE_RMEM_H_ */
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