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35ac2034db
The present sbrmi module only support reporting power via hwmon. However, AMD data center range of processors support various system management functionality using custom protocols defined in Advanced Platform Management Link (APML) specification. Register a miscdevice, which creates a device /dev/sbrmiX with an IOCTL interface for the user space to invoke the APML Mailbox protocol, which is already defined in sbrmi_mailbox_xfer(). The APML protocols depend on a set of RMI registers. Having an IOCTL as a single entry point will help in providing synchronization among these protocols as multiple transactions on RMI register set may create race condition. Support for other protocols will be added in subsequent patches. APML mailbox protocol returns additional error codes written by SMU firmware in the out-bound register 0x37. These errors include, invalid core, message not supported over platform and others. This additional error codes can be used to provide more details to user space. Open-sourced and widely used https://github.com/amd/esmi_oob_library will continue to provide user-space programmable API. Reviewed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Akshay Gupta <akshay.gupta@amd.com> Link: https://lore.kernel.org/r/20250428063034.2145566-7-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
120 lines
2.6 KiB
C
120 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* rmi-hwmon.c - hwmon sensor support for side band RMI
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*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*/
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#include <linux/err.h>
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#include <linux/hwmon.h>
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#include <uapi/misc/amd-apml.h>
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#include "rmi-core.h"
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/* Do not allow setting negative power limit */
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#define SBRMI_PWR_MIN 0
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static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct sbrmi_data *data = dev_get_drvdata(dev);
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struct apml_mbox_msg msg = { 0 };
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int ret;
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if (!data)
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return -ENODEV;
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if (type != hwmon_power)
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return -EINVAL;
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switch (attr) {
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case hwmon_power_input:
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msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION;
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ret = rmi_mailbox_xfer(data, &msg);
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break;
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case hwmon_power_cap:
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msg.cmd = SBRMI_READ_PKG_PWR_LIMIT;
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ret = rmi_mailbox_xfer(data, &msg);
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break;
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case hwmon_power_cap_max:
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msg.mb_in_out = data->pwr_limit_max;
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ret = 0;
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break;
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default:
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return -EINVAL;
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}
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if (ret < 0)
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return ret;
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/* hwmon power attributes are in microWatt */
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*val = (long)msg.mb_in_out * 1000;
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return ret;
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}
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static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long val)
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{
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struct sbrmi_data *data = dev_get_drvdata(dev);
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struct apml_mbox_msg msg = { 0 };
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if (!data)
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return -ENODEV;
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if (type != hwmon_power && attr != hwmon_power_cap)
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return -EINVAL;
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/*
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* hwmon power attributes are in microWatt
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* mailbox read/write is in mWatt
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*/
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val /= 1000;
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val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max);
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msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT;
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msg.mb_in_out = val;
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return rmi_mailbox_xfer(data, &msg);
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}
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static umode_t sbrmi_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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switch (type) {
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case hwmon_power:
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switch (attr) {
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case hwmon_power_input:
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case hwmon_power_cap_max:
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return 0444;
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case hwmon_power_cap:
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return 0644;
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}
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break;
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default:
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break;
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}
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return 0;
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}
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static const struct hwmon_channel_info * const sbrmi_info[] = {
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HWMON_CHANNEL_INFO(power,
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HWMON_P_INPUT | HWMON_P_CAP | HWMON_P_CAP_MAX),
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NULL
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};
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static const struct hwmon_ops sbrmi_hwmon_ops = {
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.is_visible = sbrmi_is_visible,
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.read = sbrmi_read,
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.write = sbrmi_write,
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};
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static const struct hwmon_chip_info sbrmi_chip_info = {
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.ops = &sbrmi_hwmon_ops,
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.info = sbrmi_info,
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};
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int create_hwmon_sensor_device(struct device *dev, struct sbrmi_data *data)
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{
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struct device *hwmon_dev;
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hwmon_dev = devm_hwmon_device_register_with_info(dev, "sbrmi", data,
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&sbrmi_chip_info, NULL);
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return PTR_ERR_OR_ZERO(hwmon_dev);
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}
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