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687cac9559
Add support for RZ/G3E xSPI. Compared to RPC-IF, it can support writes on memory-mapped area. Introduce struct rpcif_impl for holding the function pointers and data to handle the differences between xspi and rpc-if interface. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250424090000.136804-7-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* RZ xSPI Interface Registers Definitions
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*/
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#ifndef __RENESAS_XSPI_IF_REGS_H__
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#define __RENESAS_XSPI_IF_REGS_H__
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#include <linux/bits.h>
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/* xSPI Wrapper Configuration Register */
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#define XSPI_WRAPCFG 0x0000
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/* xSPI Bridge Configuration Register */
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#define XSPI_BMCFG 0x0008
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#define XSPI_BMCFG_WRMD BIT(0)
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#define XSPI_BMCFG_MWRCOMB BIT(7)
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#define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8)
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#define XSPI_BMCFG_PREEN BIT(16)
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/* xSPI Command Map Configuration Register 0 CS0 */
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#define XSPI_CMCFG0CS0 0x0010
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#define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0)
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#define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2)
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/* xSPI Command Map Configuration Register 1 CS0 */
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#define XSPI_CMCFG1CS0 0x0014
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#define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0)
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#define XSPI_CMCFG1_RDCMD_UPPER_BYTE(val) (((val) & 0xff) << 8)
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#define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16)
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/* xSPI Command Map Configuration Register 2 CS0 */
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#define XSPI_CMCFG2CS0 0x0018
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#define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0)
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#define XSPI_CMCFG2_WRCMD_UPPER(val) (((val) & 0xff) << 8)
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#define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16)
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/* xSPI Link I/O Configuration Register CS0 */
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#define XSPI_LIOCFGCS0 0x0050
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#define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0)
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#define XSPI_LIOCFG_CSMIN(val) (((val) & 0x0f) << 16)
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#define XSPI_LIOCFG_CSASTEX BIT(20)
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#define XSPI_LIOCFG_CSNEGEX BIT(21)
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/* xSPI Bridge Map Control Register 0 */
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#define XSPI_BMCTL0 0x0060
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#define XSPI_BMCTL0_CS0ACC(val) (((val) & 0x03) << 0)
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/* xSPI Bridge Map Control Register 1 */
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#define XSPI_BMCTL1 0x0064
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#define XSPI_BMCTL1_MWRPUSH BIT(8)
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/* xSPI Command Manual Control Register 0 */
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#define XSPI_CDCTL0 0x0070
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#define XSPI_CDCTL0_TRREQ BIT(0)
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#define XSPI_CDCTL0_CSSEL BIT(3)
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#define XSPI_CDCTL0_TRNUM(val) (((val) & 0x03) << 4)
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/* xSPI Command Manual Type Buf */
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#define XSPI_CDTBUF0 0x0080
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#define XSPI_CDTBUF_CMDSIZE(val) (((val) & 0x03) << 0)
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#define XSPI_CDTBUF_ADDSIZE(val) (((val) & 0x07) << 2)
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#define XSPI_CDTBUF_DATASIZE(val) (((val) & 0x0f) << 5)
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#define XSPI_CDTBUF_LATE(val) (((val) & 0x1f) << 9)
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#define XSPI_CDTBUF_TRTYPE BIT(15)
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#define XSPI_CDTBUF_CMD(val) (((val) & 0xffff) << 16)
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#define XSPI_CDTBUF_CMD_FIELD(val) (((val) & 0xff) << 24)
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/* xSPI Command Manual Address Buff */
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#define XSPI_CDABUF0 0x0084
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/* xSPI Command Manual Data 0 Buf */
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#define XSPI_CDD0BUF0 0x0088
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/* xSPI Command Manual Data 1 Buf */
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#define XSPI_CDD1BUF0 0x008c
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/* xSPI Command Calibration Control Register 0 CS0 */
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#define XSPI_CCCTL0CS0 0x0130
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#define XSPI_CCCTL0_CAEN BIT(0)
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/* xSPI Interrupt Status Register */
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#define XSPI_INTS 0x0190
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#define XSPI_INTS_CMDCMP BIT(0)
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/* xSPI Interrupt Clear Register */
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#define XSPI_INTC 0x0194
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#define XSPI_INTC_CMDCMPC BIT(0)
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/* xSPI Interrupt Enable Register */
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#define XSPI_INTE 0x0198
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#define XSPI_INTE_CMDCMPE BIT(0)
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/* Maximum data size of MWRSIZE*/
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#define MWRSIZE_MAX 64
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/* xSPI Protocol mode */
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#define PROTO_1S_2S_2S 0x48
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#define PROTO_2S_2S_2S 0x49
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#define PROTO_1S_4S_4S 0x090
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#define PROTO_4S_4S_4S 0x092
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#endif /* __RENESAS_XSPI_IF_REGS_H__ */
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