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228e72bf94
Move rpc-if reg definitions to a header file for the preparation of adding support for RZ/G3E XSPI that has different register definitions. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250424090000.136804-3-biju.das.jz@bp.renesas.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
147 lines
5.1 KiB
C
147 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car RPC Interface Registers Definitions
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*/
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#ifndef __RENESAS_RPC_IF_REGS_H__
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#define __RENESAS_RPC_IF_REGS_H__
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#include <linux/bits.h>
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#define RPCIF_CMNCR 0x0000 /* R/W */
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#define RPCIF_CMNCR_MD BIT(31)
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#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
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#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
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#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
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#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
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#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
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RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
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#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */
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#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */
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#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
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#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
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RPCIF_CMNCR_IO3FV(val))
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#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
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#define RPCIF_SSLDR 0x0004 /* R/W */
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#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
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#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
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#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
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#define RPCIF_DRCR 0x000C /* R/W */
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#define RPCIF_DRCR_SSLN BIT(24)
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#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
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#define RPCIF_DRCR_RCF BIT(9)
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#define RPCIF_DRCR_RBE BIT(8)
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#define RPCIF_DRCR_SSLE BIT(0)
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#define RPCIF_DRCMR 0x0010 /* R/W */
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#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPCIF_DREAR 0x0014 /* R/W */
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#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
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#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
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#define RPCIF_DROPR 0x0018 /* R/W */
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#define RPCIF_DRENR 0x001C /* R/W */
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#define RPCIF_DRENR_CDB(o) (((u32)((o) & 0x3)) << 30)
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#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
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#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
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#define RPCIF_DRENR_DME BIT(15)
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#define RPCIF_DRENR_CDE BIT(14)
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#define RPCIF_DRENR_OCDE BIT(12)
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#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
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#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPCIF_SMCR 0x0020 /* R/W */
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#define RPCIF_SMCR_SSLKP BIT(8)
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#define RPCIF_SMCR_SPIRE BIT(2)
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#define RPCIF_SMCR_SPIWE BIT(1)
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#define RPCIF_SMCR_SPIE BIT(0)
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#define RPCIF_SMCMR 0x0024 /* R/W */
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#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
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#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
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#define RPCIF_SMADR 0x0028 /* R/W */
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#define RPCIF_SMOPR 0x002C /* R/W */
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#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
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#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
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#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
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#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
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#define RPCIF_SMENR 0x0030 /* R/W */
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#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
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#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
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#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
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#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
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#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
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#define RPCIF_SMENR_DME BIT(15)
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#define RPCIF_SMENR_CDE BIT(14)
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#define RPCIF_SMENR_OCDE BIT(12)
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#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
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#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
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#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
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#define RPCIF_SMRDR0 0x0038 /* R */
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#define RPCIF_SMRDR1 0x003C /* R */
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#define RPCIF_SMWDR0 0x0040 /* W */
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#define RPCIF_SMWDR1 0x0044 /* W */
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#define RPCIF_CMNSR 0x0048 /* R */
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#define RPCIF_CMNSR_SSLF BIT(1)
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#define RPCIF_CMNSR_TEND BIT(0)
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#define RPCIF_DRDMCR 0x0058 /* R/W */
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#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
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#define RPCIF_DRDRENR 0x005C /* R/W */
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#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
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#define RPCIF_DRDRENR_ADDRE BIT(8)
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#define RPCIF_DRDRENR_OPDRE BIT(4)
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#define RPCIF_DRDRENR_DRDRE BIT(0)
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#define RPCIF_SMDMCR 0x0060 /* R/W */
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#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
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#define RPCIF_SMDRENR 0x0064 /* R/W */
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#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
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#define RPCIF_SMDRENR_ADDRE BIT(8)
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#define RPCIF_SMDRENR_OPDRE BIT(4)
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#define RPCIF_SMDRENR_SPIDRE BIT(0)
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#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
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#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
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#define RPCIF_PHYCNT 0x007C /* R/W */
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#define RPCIF_PHYCNT_CAL BIT(31)
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#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
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#define RPCIF_PHYCNT_EXDS BIT(21)
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#define RPCIF_PHYCNT_OCT BIT(20)
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#define RPCIF_PHYCNT_DDRCAL BIT(19)
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#define RPCIF_PHYCNT_HS BIT(18)
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#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
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#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
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#define RPCIF_PHYCNT_WBUF2 BIT(4)
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#define RPCIF_PHYCNT_WBUF BIT(2)
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#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
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#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
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#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
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#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
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#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
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#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
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#define RPCIF_PHYINT 0x0088 /* R/W */
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#define RPCIF_PHYINT_WPVAL BIT(1)
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#endif /* __RENESAS_RPC_IF_REGS_H__ */
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