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f759b8fd30
The get hw version and src pad code functions can be common code in csid core file, then the csid driver of different hw version can reuse them, rather than adding duplicate code in csid driver for each version. Suggested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
432 lines
13 KiB
C
432 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* camss-csid-4-7.c
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*
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* Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
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*
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* Copyright (C) 2020 Linaro Ltd.
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*/
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include "camss-csid.h"
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#include "camss-csid-gen2.h"
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#include "camss.h"
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/* The CSID 2 IP-block is different from the others,
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* and is of a bare-bones Lite version, with no PIX
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* interface support. As a result of that it has an
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* alternate register layout.
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*/
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#define CSID_RST_STROBES 0x10
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#define RST_STROBES 0
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#define CSID_CSI2_RX_IRQ_STATUS 0x20
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#define CSID_CSI2_RX_IRQ_MASK 0x24
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#define CSID_CSI2_RX_IRQ_CLEAR 0x28
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#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) ((csid_is_lite(csid) ? 0x30 : 0x40) \
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+ 0x10 * (rdi))
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#define CSID_CSI2_RDIN_IRQ_MASK(rdi) ((csid_is_lite(csid) ? 0x34 : 0x44) \
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+ 0x10 * (rdi))
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#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) ((csid_is_lite(csid) ? 0x38 : 0x48) \
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+ 0x10 * (rdi))
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#define CSID_CSI2_RDIN_IRQ_SET(rdi) ((csid_is_lite(csid) ? 0x3C : 0x4C) \
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+ 0x10 * (rdi))
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#define CSID_TOP_IRQ_STATUS 0x70
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#define TOP_IRQ_STATUS_RESET_DONE 0
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#define CSID_TOP_IRQ_MASK 0x74
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#define CSID_TOP_IRQ_CLEAR 0x78
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#define CSID_TOP_IRQ_SET 0x7C
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#define CSID_IRQ_CMD 0x80
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#define IRQ_CMD_CLEAR 0
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#define IRQ_CMD_SET 4
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#define CSID_CSI2_RX_CFG0 0x100
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#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
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#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
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#define CSI2_RX_CFG0_DL1_INPUT_SEL 8
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#define CSI2_RX_CFG0_DL2_INPUT_SEL 12
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#define CSI2_RX_CFG0_DL3_INPUT_SEL 16
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#define CSI2_RX_CFG0_PHY_NUM_SEL 20
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#define CSI2_RX_CFG0_PHY_TYPE_SEL 24
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#define CSID_CSI2_RX_CFG1 0x104
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#define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN 0
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#define CSI2_RX_CFG1_DE_SCRAMBLE_EN 1
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#define CSI2_RX_CFG1_VC_MODE 2
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#define CSI2_RX_CFG1_COMPLETE_STREAM_EN 4
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#define CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING 5
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#define CSI2_RX_CFG1_MISR_EN 6
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#define CSI2_RX_CFG1_CGC_MODE 7
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#define CGC_MODE_DYNAMIC_GATING 0
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#define CGC_MODE_ALWAYS_ON 1
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#define CSID_RDI_CFG0(rdi) ((csid_is_lite(csid) ? 0x200 : 0x300) \
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+ 0x100 * (rdi))
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#define RDI_CFG0_BYTE_CNTR_EN 0
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#define RDI_CFG0_FORMAT_MEASURE_EN 1
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#define RDI_CFG0_TIMESTAMP_EN 2
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#define RDI_CFG0_DROP_H_EN 3
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#define RDI_CFG0_DROP_V_EN 4
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#define RDI_CFG0_CROP_H_EN 5
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#define RDI_CFG0_CROP_V_EN 6
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#define RDI_CFG0_MISR_EN 7
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#define RDI_CFG0_CGC_MODE 8
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#define CGC_MODE_DYNAMIC 0
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#define CGC_MODE_ALWAYS_ON 1
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#define RDI_CFG0_PLAIN_ALIGNMENT 9
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#define PLAIN_ALIGNMENT_LSB 0
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#define PLAIN_ALIGNMENT_MSB 1
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#define RDI_CFG0_PLAIN_FORMAT 10
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#define RDI_CFG0_DECODE_FORMAT 12
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#define RDI_CFG0_DATA_TYPE 16
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#define RDI_CFG0_VIRTUAL_CHANNEL 22
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#define RDI_CFG0_DT_ID 27
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#define RDI_CFG0_EARLY_EOF_EN 29
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#define RDI_CFG0_PACKING_FORMAT 30
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#define RDI_CFG0_ENABLE 31
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#define CSID_RDI_CFG1(rdi) ((csid_is_lite(csid) ? 0x204 : 0x304)\
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+ 0x100 * (rdi))
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#define RDI_CFG1_TIMESTAMP_STB_SEL 0
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#define CSID_RDI_CTRL(rdi) ((csid_is_lite(csid) ? 0x208 : 0x308)\
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+ 0x100 * (rdi))
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#define RDI_CTRL_HALT_CMD 0
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#define HALT_CMD_HALT_AT_FRAME_BOUNDARY 0
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#define HALT_CMD_RESUME_AT_FRAME_BOUNDARY 1
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#define RDI_CTRL_HALT_MODE 2
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#define CSID_RDI_FRM_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x20C : 0x30C)\
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+ 0x100 * (rdi))
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#define CSID_RDI_FRM_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x210 : 0x310)\
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+ 0x100 * (rdi))
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#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) ((csid_is_lite(csid) ? 0x214 : 0x314)\
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+ 0x100 * (rdi))
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#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) ((csid_is_lite(csid) ? 0x218 : 0x318)\
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+ 0x100 * (rdi))
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#define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x224 : 0x324)\
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+ 0x100 * (rdi))
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#define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x228 : 0x328)\
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+ 0x100 * (rdi))
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#define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x22C : 0x32C)\
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+ 0x100 * (rdi))
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#define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x230 : 0x330)\
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+ 0x100 * (rdi))
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#define CSID_TPG_CTRL 0x600
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#define TPG_CTRL_TEST_EN 0
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#define TPG_CTRL_FS_PKT_EN 1
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#define TPG_CTRL_FE_PKT_EN 2
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#define TPG_CTRL_NUM_ACTIVE_LANES 4
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#define TPG_CTRL_CYCLES_BETWEEN_PKTS 8
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#define TPG_CTRL_NUM_TRAIL_BYTES 20
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#define CSID_TPG_VC_CFG0 0x604
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#define TPG_VC_CFG0_VC_NUM 0
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#define TPG_VC_CFG0_NUM_ACTIVE_SLOTS 8
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#define NUM_ACTIVE_SLOTS_0_ENABLED 0
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#define NUM_ACTIVE_SLOTS_0_1_ENABLED 1
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#define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2
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#define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3
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#define TPG_VC_CFG0_LINE_INTERLEAVING_MODE 10
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#define INTELEAVING_MODE_INTERLEAVED 0
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#define INTELEAVING_MODE_ONE_SHOT 1
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#define TPG_VC_CFG0_NUM_FRAMES 16
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#define CSID_TPG_VC_CFG1 0x608
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#define TPG_VC_CFG1_H_BLANKING_COUNT 0
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#define TPG_VC_CFG1_V_BLANKING_COUNT 12
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#define TPG_VC_CFG1_V_BLANK_FRAME_WIDTH_SEL 24
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#define CSID_TPG_LFSR_SEED 0x60C
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#define CSID_TPG_DT_n_CFG_0(n) (0x610 + (n) * 0xC)
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#define TPG_DT_n_CFG_0_FRAME_HEIGHT 0
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#define TPG_DT_n_CFG_0_FRAME_WIDTH 16
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#define CSID_TPG_DT_n_CFG_1(n) (0x614 + (n) * 0xC)
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#define TPG_DT_n_CFG_1_DATA_TYPE 0
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#define TPG_DT_n_CFG_1_ECC_XOR_MASK 8
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#define TPG_DT_n_CFG_1_CRC_XOR_MASK 16
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#define CSID_TPG_DT_n_CFG_2(n) (0x618 + (n) * 0xC)
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#define TPG_DT_n_CFG_2_PAYLOAD_MODE 0
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#define TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD 4
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#define TPG_DT_n_CFG_2_ENCODE_FORMAT 16
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#define CSID_TPG_COLOR_BARS_CFG 0x640
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#define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN 0
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#define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_SEL 4
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#define TPG_COLOR_BARS_CFG_SPLIT_EN 5
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#define TPG_COLOR_BARS_CFG_ROTATE_PERIOD 8
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#define CSID_TPG_COLOR_BOX_CFG 0x644
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#define TPG_COLOR_BOX_CFG_MODE 0
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#define TPG_COLOR_BOX_PATTERN_SEL 2
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static void __csid_configure_rx(struct csid_device *csid,
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struct csid_phy_config *phy, int vc)
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{
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u8 lane_cnt = csid->phy.lane_cnt;
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int val;
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if (!lane_cnt)
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lane_cnt = 4;
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val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
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val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
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val |= phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL;
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
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val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
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if (vc > 3)
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val |= 1 << CSI2_RX_CFG1_VC_MODE;
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val |= 1 << CSI2_RX_CFG1_MISR_EN;
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writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
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}
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static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
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{
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int val;
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if (enable)
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val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
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else
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val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
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writel_relaxed(val, csid->base + CSID_RDI_CTRL(rdi));
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}
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static void __csid_configure_testgen(struct csid_device *csid, u8 enable, u8 vc)
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{
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struct csid_testgen_config *tg = &csid->testgen;
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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u8 lane_cnt = csid->phy.lane_cnt;
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u32 val;
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if (!lane_cnt)
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lane_cnt = 4;
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/* configure one DT, infinite frames */
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val = vc << TPG_VC_CFG0_VC_NUM;
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val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
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val |= 0 << TPG_VC_CFG0_NUM_FRAMES;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
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val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;
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val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;
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writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
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writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
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val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
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val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
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val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
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val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
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val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
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val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
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writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
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writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
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val = enable << TPG_CTRL_TEST_EN;
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val |= 1 << TPG_CTRL_FS_PKT_EN;
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val |= 1 << TPG_CTRL_FE_PKT_EN;
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val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;
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val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;
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val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;
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writel_relaxed(val, csid->base + CSID_TPG_CTRL);
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}
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static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
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{
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/* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
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struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
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const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
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csid->res->formats->nformats,
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input_format->code);
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u32 val;
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/*
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* DT_ID is a two bit bitfield that is concatenated with
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* the four least significant bits of the five bit VC
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* bitfield to generate an internal CID value.
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*
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* CSID_RDI_CFG0(vc)
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* DT_ID : 28:27
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* VC : 26:22
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* DT : 21:16
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*
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* CID : VC 3:0 << 2 | DT_ID 1:0
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*/
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u8 dt_id = vc & 0x03;
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val = 1 << RDI_CFG0_BYTE_CNTR_EN;
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val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;
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val |= 1 << RDI_CFG0_TIMESTAMP_EN;
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/* note: for non-RDI path, this should be format->decode_format */
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val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
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val |= format->data_type << RDI_CFG0_DATA_TYPE;
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val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
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val |= dt_id << RDI_CFG0_DT_ID;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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/* CSID_TIMESTAMP_STB_POST_IRQ */
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val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;
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writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
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val = 1;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
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val = 0;
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writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
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val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));
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val |= enable << RDI_CFG0_ENABLE;
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writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
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}
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static void csid_configure_stream(struct csid_device *csid, u8 enable)
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{
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struct csid_testgen_config *tg = &csid->testgen;
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u8 i;
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/* Loop through all enabled VCs and configure stream for each */
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for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
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if (csid->phy.en_vc & BIT(i)) {
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if (tg->enabled)
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__csid_configure_testgen(csid, enable, i);
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__csid_configure_rdi_stream(csid, enable, i);
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__csid_configure_rx(csid, &csid->phy, i);
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__csid_ctrl_rdi(csid, enable, i);
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}
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}
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static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
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{
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if (val > 0 && val <= csid->testgen.nmodes)
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csid->testgen.mode = val;
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return 0;
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}
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/*
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* csid_isr - CSID module interrupt service routine
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* @irq: Interrupt line
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* @dev: CSID device
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*
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* Return IRQ_HANDLED on success
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*/
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static irqreturn_t csid_isr(int irq, void *dev)
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{
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struct csid_device *csid = dev;
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u32 val;
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u8 reset_done;
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int i;
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val = readl_relaxed(csid->base + CSID_TOP_IRQ_STATUS);
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writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR);
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reset_done = val & BIT(TOP_IRQ_STATUS_RESET_DONE);
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val = readl_relaxed(csid->base + CSID_CSI2_RX_IRQ_STATUS);
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writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
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/* Read and clear IRQ status for each enabled RDI channel */
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for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
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if (csid->phy.en_vc & BIT(i)) {
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val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
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writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
|
|
}
|
|
|
|
val = 1 << IRQ_CMD_CLEAR;
|
|
writel_relaxed(val, csid->base + CSID_IRQ_CMD);
|
|
|
|
if (reset_done)
|
|
complete(&csid->reset_complete);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*
|
|
* csid_reset - Trigger reset on CSID module and wait to complete
|
|
* @csid: CSID device
|
|
*
|
|
* Return 0 on success or a negative error code otherwise
|
|
*/
|
|
static int csid_reset(struct csid_device *csid)
|
|
{
|
|
unsigned long time;
|
|
u32 val;
|
|
|
|
reinit_completion(&csid->reset_complete);
|
|
|
|
writel_relaxed(1, csid->base + CSID_TOP_IRQ_CLEAR);
|
|
writel_relaxed(1, csid->base + CSID_IRQ_CMD);
|
|
writel_relaxed(1, csid->base + CSID_TOP_IRQ_MASK);
|
|
writel_relaxed(1, csid->base + CSID_IRQ_CMD);
|
|
|
|
/* preserve registers */
|
|
val = 0x1e << RST_STROBES;
|
|
writel_relaxed(val, csid->base + CSID_RST_STROBES);
|
|
|
|
time = wait_for_completion_timeout(&csid->reset_complete,
|
|
msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
|
|
if (!time) {
|
|
dev_err(csid->camss->dev, "CSID reset timeout\n");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void csid_subdev_init(struct csid_device *csid)
|
|
{
|
|
csid->testgen.modes = csid_testgen_modes;
|
|
csid->testgen.nmodes = CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN2;
|
|
}
|
|
|
|
const struct csid_hw_ops csid_ops_gen2 = {
|
|
.configure_stream = csid_configure_stream,
|
|
.configure_testgen_pattern = csid_configure_testgen_pattern,
|
|
.hw_version = csid_hw_version,
|
|
.isr = csid_isr,
|
|
.reset = csid_reset,
|
|
.src_pad_code = csid_src_pad_code,
|
|
.subdev_init = csid_subdev_init,
|
|
};
|