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a1e2940458
This adds support for stateful V4L2 M2M based driver for Imagination E5010 JPEG Encoder [1] which supports baseline encoding with two different quantization tables and compression ratio as demanded. Support for both contiguous and non-contiguous YUV420 and YUV422 semiplanar formats is added along with alignment restrictions as required by the hardware. System and runtime PM hooks are added in the driver along with v4l2 crop and selection API support. Minimum resolution supported is 64x64 and Maximum resolution supported is 8192x8192. All v4l2-compliance tests are passing [2] : v4l2-compliance -s -f -a -d /dev/video0 -e /dev/video1 Total for e5010 device /dev/video0: 79, Succeeded: 79, Failed: 0, Warnings: 0 NOTE: video1 here is VIVID test pattern generator Also tests [3] were run manually to verify below driver features: - Runtime Power Management - Multi-instance JPEG Encoding - DMABUF import, export support - NV12, NV21, NV16, NV61 video format support - Compression quality S_CTRL - Cropping support using S_SELECTION Existing V4L2 M2M based JPEG drivers namely s5p-jpeg, imx-jpeg and rcar_jpu were referred while making this. TODO: Add MMU and memory tiling support [1]: AM62A TRM (Section 7.6 is for JPEG Encoder) : Link: https://www.ti.com/lit/pdf/spruj16 [2]: v4l2-compliance test : Link: https://gist.github.com/devarsht/1f039c631ca953a57f405cfce1b69e49 [3]: E5010 JPEG Encoder Manual tests : Performance: Link: https://gist.github.com/devarsht/c40672944fd71c9a53ab55adbfd9e28b Functionality: Link: https://gist.github.com/devarsht/8e88fcaabff016bb2bac83d89c9d23ce Compression Quality: Link: https://gist.github.com/devarsht/cbcc7cd97e8c48ba1486caa2b7884655 Multi Instance: Link: https://gist.github.com/devarsht/22c2fca08cd3441fb40f2c7a4cebc95a Crop support: Link: https://gist.github.com/devarsht/de6f5142f678bb1a5338abfd9f814abd Runtime PM: Link: https://gist.github.com/devarsht/70cd95d4440ddc678489d93885ddd4dd Co-developed-by: David Huang <d-huang@ti.com> Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
311 lines
11 KiB
C
311 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Imagination E5010 JPEG Encoder driver.
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*
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Author: David Huang <d-huang@ti.com>
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* Author: Devarsh Thakkar <devarsht@ti.com>
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*/
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#ifndef _E5010_MMU_REGS_H
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#define _E5010_MMU_REGS_H
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#define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)
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#define MMU_MMU_DIR_BASE_ADDR_STRIDE (4)
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#define MMU_MMU_DIR_BASE_ADDR_NO_ENTRIES (4)
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#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)
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#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)
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#define MMU_MMU_TILE_CFG_OFFSET (0x0040)
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#define MMU_MMU_TILE_CFG_STRIDE (4)
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#define MMU_MMU_TILE_CFG_NO_ENTRIES (4)
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#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)
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#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_SHIFT (4)
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#define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)
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#define MMU_MMU_TILE_CFG_TILE_ENABLE_SHIFT (3)
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#define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)
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#define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)
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#define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)
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#define MMU_MMU_TILE_MIN_ADDR_STRIDE (4)
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#define MMU_MMU_TILE_MIN_ADDR_NO_ENTRIES (4)
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#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFFF)
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#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_SHIFT (0)
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#define MMU_MMU_TILE_MAX_ADDR_OFFSET (0x0060)
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#define MMU_MMU_TILE_MAX_ADDR_STRIDE (4)
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#define MMU_MMU_TILE_MAX_ADDR_NO_ENTRIES (4)
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#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_MASK (0xFFFFFFFF)
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#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_SHIFT (0)
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#define MMU_MMU_CONTROL0_OFFSET (0x0000)
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#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_MASK (0x00000001)
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#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_SHIFT (0)
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#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_MASK (0x00000100)
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#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_SHIFT (8)
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#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_MASK (0x00000200)
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#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_SHIFT (9)
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#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_MASK (0x00001000)
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#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_SHIFT (12)
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#define MMU_MMU_CONTROL1_OFFSET (0x0008)
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#define MMU_MMU_CONTROL1_MMU_FLUSH_MASK (0x00000008)
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#define MMU_MMU_CONTROL1_MMU_FLUSH_SHIFT (3)
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#define MMU_MMU_CONTROL1_MMU_FLUSH_NO_REPS (4)
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#define MMU_MMU_CONTROL1_MMU_FLUSH_SIZE (1)
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#define MMU_MMU_CONTROL1_MMU_INVALDC_MASK (0x00000800)
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#define MMU_MMU_CONTROL1_MMU_INVALDC_SHIFT (11)
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#define MMU_MMU_CONTROL1_MMU_INVALDC_NO_REPS (4)
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#define MMU_MMU_CONTROL1_MMU_INVALDC_SIZE (1)
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#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_MASK (0x00010000)
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#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_SHIFT (16)
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#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_MASK (0x00100000)
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#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_SHIFT (20)
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#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_MASK (0x01000000)
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#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_SHIFT (24)
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#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_MASK (0x02000000)
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#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_SHIFT (25)
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#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK (0x10000000)
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#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT (28)
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#define MMU_MMU_BANK_INDEX_OFFSET (0x0010)
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#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_MASK (0xC0000000)
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#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SHIFT (30)
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#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_NO_REPS (16)
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#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SIZE (2)
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#define MMU_REQUEST_PRIORITY_ENABLE_OFFSET (0x0018)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_MASK (0x00008000)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SHIFT (15)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_NO_REPS (16)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SIZE (1)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_MASK (0x00010000)
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#define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_SHIFT (16)
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#define MMU_REQUEST_LIMITED_THROUGHPUT_OFFSET (0x001C)
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#define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_MASK (0x000003FF)
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#define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_SHIFT (0)
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#define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_MASK (0x0FFF0000)
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#define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_SHIFT (16)
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#define MMU_MMU_ADDRESS_CONTROL_OFFSET (0x0070)
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#define MMU_MMU_ADDRESS_CONTROL_TRUSTED (IMG_TRUE)
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#define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK (0x00000001)
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#define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT (0)
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#define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_MASK (0x00000010)
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#define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_SHIFT (4)
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#define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_MASK (0x00FF0000)
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#define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_SHIFT (16)
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#define MMU_MMU_CONFIG0_OFFSET (0x0080)
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#define MMU_MMU_CONFIG0_NUM_REQUESTORS_MASK (0x0000000F)
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#define MMU_MMU_CONFIG0_NUM_REQUESTORS_SHIFT (0)
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#define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_MASK (0x000000F0)
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#define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_SHIFT (4)
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#define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_MASK (0x00000700)
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#define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_SHIFT (8)
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#define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_MASK (0x00001000)
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#define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_SHIFT (12)
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#define MMU_MMU_CONFIG0_MMU_SUPPORTED_MASK (0x00002000)
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#define MMU_MMU_CONFIG0_MMU_SUPPORTED_SHIFT (13)
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#define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_MASK (0x001F0000)
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#define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_SHIFT (16)
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#define MMU_MMU_CONFIG0_NO_READ_REORDER_MASK (0x00200000)
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#define MMU_MMU_CONFIG0_NO_READ_REORDER_SHIFT (21)
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#define MMU_MMU_CONFIG0_TAGS_SUPPORTED_MASK (0xFFC00000)
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#define MMU_MMU_CONFIG0_TAGS_SUPPORTED_SHIFT (22)
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#define MMU_MMU_CONFIG1_OFFSET (0x0084)
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#define MMU_MMU_CONFIG1_PAGE_SIZE_MASK (0x0000000F)
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#define MMU_MMU_CONFIG1_PAGE_SIZE_SHIFT (0)
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#define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_MASK (0x0000FF00)
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#define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_SHIFT (8)
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#define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_MASK (0x001F0000)
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#define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_SHIFT (16)
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#define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_MASK (0x01000000)
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#define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_SHIFT (24)
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#define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_MASK (0x02000000)
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#define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_SHIFT (25)
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#define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_MASK (0x04000000)
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#define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_SHIFT (26)
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#define MMU_MMU_STATUS0_OFFSET (0x0088)
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#define MMU_MMU_STATUS0_MMU_PF_N_RW_MASK (0x00000001)
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#define MMU_MMU_STATUS0_MMU_PF_N_RW_SHIFT (0)
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#define MMU_MMU_STATUS0_MMU_FAULT_ADDR_MASK (0xFFFFF000)
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#define MMU_MMU_STATUS0_MMU_FAULT_ADDR_SHIFT (12)
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#define MMU_MMU_STATUS1_OFFSET (0x008C)
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#define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_MASK (0x0000FFFF)
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#define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_SHIFT (0)
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#define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_MASK (0x000F0000)
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#define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_SHIFT (16)
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#define MMU_MMU_STATUS1_MMU_FAULT_INDEX_MASK (0x03000000)
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#define MMU_MMU_STATUS1_MMU_FAULT_INDEX_SHIFT (24)
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#define MMU_MMU_STATUS1_MMU_FAULT_RNW_MASK (0x10000000)
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#define MMU_MMU_STATUS1_MMU_FAULT_RNW_SHIFT (28)
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#define MMU_MMU_MEM_REQ_OFFSET (0x0090)
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#define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_MASK (0x000003FF)
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#define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_SHIFT (0)
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#define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_MASK (0x00001000)
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#define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_SHIFT (12)
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#define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_MASK (0x00002000)
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#define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_SHIFT (13)
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#define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_MASK (0x00004000)
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#define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_SHIFT (14)
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#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_MASK (0x80000000)
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#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SHIFT (31)
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#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_NO_REPS (16)
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#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SIZE (1)
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#define MMU_MMU_FAULT_SELECT_OFFSET (0x00A0)
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#define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_MASK (0x0000000F)
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#define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_SHIFT (0)
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#define MMU_PROTOCOL_FAULT_OFFSET (0x00A8)
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#define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_MASK (0x00000001)
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#define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_SHIFT (0)
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#define MMU_PROTOCOL_FAULT_FAULT_WRITE_MASK (0x00000010)
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#define MMU_PROTOCOL_FAULT_FAULT_WRITE_SHIFT (4)
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#define MMU_PROTOCOL_FAULT_FAULT_READ_MASK (0x00000020)
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#define MMU_PROTOCOL_FAULT_FAULT_READ_SHIFT (5)
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#define MMU_TOTAL_READ_REQ_OFFSET (0x0100)
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#define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_MASK (0xFFFFFFFF)
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#define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_SHIFT (0)
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#define MMU_TOTAL_WRITE_REQ_OFFSET (0x0104)
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#define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_MASK (0xFFFFFFFF)
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#define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_SHIFT (0)
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#define MMU_READS_LESS_64_REQ_OFFSET (0x0108)
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#define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_MASK (0xFFFFFFFF)
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#define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_SHIFT (0)
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#define MMU_WRITES_LESS_64_REQ_OFFSET (0x010C)
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#define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_MASK (0xFFFFFFFF)
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#define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_SHIFT (0)
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#define MMU_EXT_CMD_STALL_OFFSET (0x0120)
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#define MMU_EXT_CMD_STALL_EXT_CMD_STALL_MASK (0xFFFFFFFF)
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#define MMU_EXT_CMD_STALL_EXT_CMD_STALL_SHIFT (0)
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#define MMU_WRITE_REQ_STALL_OFFSET (0x0124)
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#define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_MASK (0xFFFFFFFF)
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#define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_SHIFT (0)
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#define MMU_MMU_MISS_STALL_OFFSET (0x0128)
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#define MMU_MMU_MISS_STALL_MMU_MISS_STALL_MASK (0xFFFFFFFF)
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#define MMU_MMU_MISS_STALL_MMU_MISS_STALL_SHIFT (0)
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#define MMU_ADDRESS_STALL_OFFSET (0x012C)
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#define MMU_ADDRESS_STALL_ADDRESS_STALL_MASK (0xFFFFFFFF)
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#define MMU_ADDRESS_STALL_ADDRESS_STALL_SHIFT (0)
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#define MMU_TAG_STALL_OFFSET (0x0130)
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#define MMU_TAG_STALL_TAG_STALL_MASK (0xFFFFFFFF)
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#define MMU_TAG_STALL_TAG_STALL_SHIFT (0)
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#define MMU_PEAK_READ_OUTSTANDING_OFFSET (0x0140)
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#define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_MASK (0x000003FF)
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#define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_SHIFT (0)
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#define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_MASK (0xFFFF0000)
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#define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_SHIFT (16)
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#define MMU_AVERAGE_READ_LATENCY_OFFSET (0x0144)
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#define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_MASK (0xFFFFFFFF)
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#define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_SHIFT (0)
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#define MMU_STATISTICS_CONTROL_OFFSET (0x0160)
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#define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_MASK (0x00000001)
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#define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_SHIFT (0)
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#define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_MASK (0x00000002)
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#define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_SHIFT (1)
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#define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_MASK (0x00000004)
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#define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_SHIFT (2)
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#define MMU_MMU_VERSION_OFFSET (0x01D0)
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#define MMU_MMU_VERSION_MMU_MAJOR_REV_MASK (0x00FF0000)
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#define MMU_MMU_VERSION_MMU_MAJOR_REV_SHIFT (16)
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#define MMU_MMU_VERSION_MMU_MINOR_REV_MASK (0x0000FF00)
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#define MMU_MMU_VERSION_MMU_MINOR_REV_SHIFT (8)
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#define MMU_MMU_VERSION_MMU_MAINT_REV_MASK (0x000000FF)
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#define MMU_MMU_VERSION_MMU_MAINT_REV_SHIFT (0)
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#define MMU_BYTE_SIZE (0x01D4)
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#endif
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