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15568ffd59
irq_domain_add_*() interfaces are going away as being obsolete now. Switch to the preferred irq_domain_create_*() ones. Those differ in the node parameter: They take more generic struct fwnode_handle instead of struct device_node. Therefore, of_fwnode_handle() is added around the original parameter. Note some of the users can likely use dev->fwnode directly instead of indirect of_fwnode_handle(dev->of_node). But dev->fwnode is not guaranteed to be set for all, so this has to be investigated on case to case basis (by people who can actually test with the HW). [ tglx: Split out from combo patch to avoid merge conflicts ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-22-jirislaby@kernel.org
251 lines
6.1 KiB
C
251 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* arch/arm/mach-vt8500/irq.c
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*/
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/*
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* This file is copied and modified from the original irq.c provided by
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* Alexey Charkov. Minor changes have been made for Device Tree Support.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define VT8500_ICPC_IRQ 0x20
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#define VT8500_ICPC_FIQ 0x24
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#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
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#define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
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/* ICPC */
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#define ICPC_MASK 0x3F
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#define ICPC_ROTATE BIT(6)
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/* IC_DCTR */
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#define ICDC_IRQ 0x00
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#define ICDC_FIQ 0x01
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#define ICDC_DSS0 0x02
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#define ICDC_DSS1 0x03
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#define ICDC_DSS2 0x04
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#define ICDC_DSS3 0x05
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#define ICDC_DSS4 0x06
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#define ICDC_DSS5 0x07
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#define VT8500_INT_DISABLE 0
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#define VT8500_INT_ENABLE BIT(3)
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#define VT8500_TRIGGER_HIGH 0
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#define VT8500_TRIGGER_RISING BIT(5)
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#define VT8500_TRIGGER_FALLING BIT(6)
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#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
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| VT8500_TRIGGER_FALLING)
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/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
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#define VT8500_INTC_MAX 2
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struct vt8500_irq_data {
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void __iomem *base; /* IO Memory base address */
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struct irq_domain *domain; /* Domain for this controller */
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};
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/* Primary interrupt controller data */
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static struct vt8500_irq_data *primary_intc;
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static void vt8500_irq_ack(struct irq_data *d)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
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u32 status = (1 << (d->hwirq & 0x1f));
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writel(status, stat_reg);
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}
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static void vt8500_irq_mask(struct irq_data *d)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr &= ~VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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}
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static void vt8500_irq_unmask(struct irq_data *d)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr |= VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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}
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static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr &= ~VT8500_EDGE;
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switch (flow_type) {
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case IRQF_TRIGGER_LOW:
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return -EINVAL;
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case IRQF_TRIGGER_HIGH:
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dctr |= VT8500_TRIGGER_HIGH;
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irq_set_handler_locked(d, handle_level_irq);
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break;
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case IRQF_TRIGGER_FALLING:
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dctr |= VT8500_TRIGGER_FALLING;
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irq_set_handler_locked(d, handle_edge_irq);
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break;
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case IRQF_TRIGGER_RISING:
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dctr |= VT8500_TRIGGER_RISING;
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irq_set_handler_locked(d, handle_edge_irq);
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break;
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}
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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return 0;
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}
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static struct irq_chip vt8500_irq_chip = {
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.name = "vt8500",
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.irq_ack = vt8500_irq_ack,
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.irq_mask = vt8500_irq_mask,
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.irq_unmask = vt8500_irq_unmask,
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.irq_set_type = vt8500_irq_set_type,
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};
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static void __init vt8500_init_irq_hw(void __iomem *base)
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{
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u32 i;
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/* Enable rotating priority for IRQ */
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writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
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writel(0x00, base + VT8500_ICPC_FIQ);
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/* Disable all interrupts and route them to IRQ */
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for (i = 0; i < 64; i++)
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writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
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}
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static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops vt8500_irq_domain_ops = {
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.map = vt8500_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static inline void vt8500_handle_irq_common(struct vt8500_irq_data *intc)
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{
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unsigned long irqnr = readl_relaxed(intc->base) & 0x3F;
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unsigned long stat;
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/*
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* Highest Priority register default = 63, so check that this
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* is a real interrupt by checking the status register
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*/
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if (irqnr == 63) {
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stat = readl_relaxed(intc->base + VT8500_ICIS + 4);
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if (!(stat & BIT(31)))
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return;
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}
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generic_handle_domain_irq(intc->domain, irqnr);
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}
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static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
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{
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vt8500_handle_irq_common(primary_intc);
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}
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static void vt8500_handle_irq_chained(struct irq_desc *desc)
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{
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struct irq_domain *d = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct vt8500_irq_data *intc = d->host_data;
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chained_irq_enter(chip, desc);
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vt8500_handle_irq_common(intc);
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chained_irq_exit(chip, desc);
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}
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static int __init vt8500_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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struct vt8500_irq_data *intc;
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int irq, i, ret = 0;
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intc = kzalloc(sizeof(*intc), GFP_KERNEL);
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if (!intc)
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return -ENOMEM;
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intc->base = of_iomap(node, 0);
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if (!intc->base) {
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pr_err("%s: Unable to map IO memory\n", __func__);
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ret = -ENOMEM;
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goto err_free;
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}
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intc->domain = irq_domain_create_linear(of_fwnode_handle(node), 64,
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&vt8500_irq_domain_ops, intc);
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if (!intc->domain) {
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pr_err("%s: Unable to add irq domain!\n", __func__);
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ret = -ENOMEM;
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goto err_unmap;
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}
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vt8500_init_irq_hw(intc->base);
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pr_info("vt8500-irq: Added interrupt controller\n");
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/* check if this is a chained controller */
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if (of_irq_count(node) != 0) {
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for (i = 0; i < of_irq_count(node); i++) {
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irq = irq_of_parse_and_map(node, i);
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irq_set_chained_handler_and_data(irq, vt8500_handle_irq_chained,
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intc);
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}
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pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
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} else {
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primary_intc = intc;
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set_handle_irq(vt8500_handle_irq);
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}
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return 0;
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err_unmap:
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iounmap(intc->base);
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err_free:
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kfree(intc);
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return ret;
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}
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IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
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