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8ab67b37b8
The ad354xr requires DSPI mode (2 data lanes) to work in buffering
mode, so, depending on the DAC type, target TRANSFER_REGISTER
"MULTI_IO_MODE" bitfield can be set between:
SPI (configuration, entire ad35xxr family),
DSPI (ad354xr),
QSPI (ad355xr).
Also bus IO_MODE must be set accordingly.
About removal of AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER, according to
the HDL history the flag has never been used. So looks like the driver
was including it by mistake or in anticipation for something that was
never implemented on HDL side.
Current HDL updated documentation confirm it is actually not in use
anymore and replaced by the IO_MODE bits.
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250114-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v4-4-979402e33545@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
27 lines
732 B
C
27 lines
732 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2024 Analog Devices Inc.
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* Copyright (c) 2024 Baylibre, SAS
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*/
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#ifndef __LINUX_PLATFORM_DATA_AD3552R_HS_H__
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#define __LINUX_PLATFORM_DATA_AD3552R_HS_H__
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struct iio_backend;
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enum ad3552r_io_mode {
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AD3552R_IO_MODE_SPI,
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AD3552R_IO_MODE_DSPI,
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AD3552R_IO_MODE_QSPI,
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};
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struct ad3552r_hs_platform_data {
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int (*bus_reg_read)(struct iio_backend *back, u32 reg, u32 *val,
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size_t data_size);
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int (*bus_reg_write)(struct iio_backend *back, u32 reg, u32 val,
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size_t data_size);
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int (*bus_set_io_mode)(struct iio_backend *back,
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enum ad3552r_io_mode mode);
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u32 bus_sample_data_clock_hz;
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};
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#endif /* __LINUX_PLATFORM_DATA_AD3552R_HS_H__ */
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