mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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090c3a4a26
This ensures we get all information we need to debug issues when users forward us their logs. Signed-off-by: Hector Martin <marcan@marcan.st> Reviewed-by: Neal Gompa <neal@gompa.dev> Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Sven Peter <sven@svenpeter.dev> Link: https://lore.kernel.org/r/20250427-pasemi-fixes-v3-4-af28568296c0@svenpeter.dev Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
465 lines
11 KiB
C
465 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* SMBus host driver for PA Semi PWRficient
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*/
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#include <linux/bits.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include "i2c-pasemi-core.h"
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/* Register offsets */
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#define REG_MTXFIFO 0x00
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#define REG_MRXFIFO 0x04
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#define REG_XFSTA 0x0c
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#define REG_SMSTA 0x14
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#define REG_IMASK 0x18
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#define REG_CTL 0x1c
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#define REG_REV 0x28
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/* Register defs */
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#define MTXFIFO_READ BIT(10)
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#define MTXFIFO_STOP BIT(9)
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#define MTXFIFO_START BIT(8)
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#define MTXFIFO_DATA_M GENMASK(7, 0)
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#define MRXFIFO_EMPTY BIT(8)
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#define MRXFIFO_DATA_M GENMASK(7, 0)
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#define SMSTA_XIP BIT(28)
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#define SMSTA_XEN BIT(27)
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#define SMSTA_JMD BIT(25)
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#define SMSTA_JAM BIT(24)
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#define SMSTA_MTO BIT(23)
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#define SMSTA_MTA BIT(22)
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#define SMSTA_MTN BIT(21)
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#define SMSTA_MRNE BIT(19)
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#define SMSTA_MTE BIT(16)
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#define SMSTA_TOM BIT(6)
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#define CTL_EN BIT(11)
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#define CTL_MRR BIT(10)
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#define CTL_MTR BIT(9)
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#define CTL_UJM BIT(8)
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#define CTL_CLK_M GENMASK(7, 0)
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/*
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* The hardware (supposedly) has a 25ms timeout for clock stretching, thus
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* use 100ms here which should be plenty.
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*/
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#define PASEMI_TRANSFER_TIMEOUT_MS 100
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static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
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{
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dev_dbg(smbus->dev, "smbus write reg %x val %08x\n", reg, val);
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iowrite32(val, smbus->ioaddr + reg);
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}
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static inline int reg_read(struct pasemi_smbus *smbus, int reg)
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{
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int ret;
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ret = ioread32(smbus->ioaddr + reg);
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dev_dbg(smbus->dev, "smbus read reg %x val %08x\n", reg, ret);
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return ret;
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}
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#define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
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#define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
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static void pasemi_reset(struct pasemi_smbus *smbus)
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{
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u32 val = (CTL_MTR | CTL_MRR | CTL_UJM | (smbus->clk_div & CTL_CLK_M));
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if (smbus->hw_rev >= 6)
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val |= CTL_EN;
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reg_write(smbus, REG_CTL, val);
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reinit_completion(&smbus->irq_completion);
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}
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static int pasemi_smb_clear(struct pasemi_smbus *smbus)
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{
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unsigned int status;
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int ret;
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/* First wait for the bus to go idle */
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ret = readx_poll_timeout(ioread32, smbus->ioaddr + REG_SMSTA,
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status, !(status & (SMSTA_XIP | SMSTA_JAM)),
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USEC_PER_MSEC,
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USEC_PER_MSEC * PASEMI_TRANSFER_TIMEOUT_MS);
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if (ret < 0) {
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dev_err(smbus->dev, "Bus is still stuck (status 0x%08x xfstatus 0x%08x)\n",
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status, reg_read(smbus, REG_XFSTA));
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return -EIO;
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}
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/* If any badness happened or there is data in the FIFOs, reset the FIFOs */
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if ((status & (SMSTA_MRNE | SMSTA_JMD | SMSTA_MTO | SMSTA_TOM | SMSTA_MTN | SMSTA_MTA)) ||
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!(status & SMSTA_MTE)) {
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dev_warn(smbus->dev, "Issuing reset due to status 0x%08x (xfstatus 0x%08x)\n",
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status, reg_read(smbus, REG_XFSTA));
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pasemi_reset(smbus);
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}
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/* Clear the flags */
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reg_write(smbus, REG_SMSTA, status);
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return 0;
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}
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static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
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{
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unsigned int status;
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if (smbus->use_irq) {
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reinit_completion(&smbus->irq_completion);
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reg_write(smbus, REG_IMASK, SMSTA_XEN | SMSTA_MTN);
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int ret = wait_for_completion_timeout(
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&smbus->irq_completion,
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msecs_to_jiffies(PASEMI_TRANSFER_TIMEOUT_MS));
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reg_write(smbus, REG_IMASK, 0);
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status = reg_read(smbus, REG_SMSTA);
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if (ret < 0) {
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dev_err(smbus->dev,
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"Completion wait failed with %d, status 0x%08x\n",
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ret, status);
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return ret;
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} else if (ret == 0) {
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dev_err(smbus->dev, "Timeout, status 0x%08x\n", status);
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return -ETIME;
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}
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} else {
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int ret = readx_poll_timeout(
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ioread32, smbus->ioaddr + REG_SMSTA,
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status, status & SMSTA_XEN,
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USEC_PER_MSEC,
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USEC_PER_MSEC * PASEMI_TRANSFER_TIMEOUT_MS);
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if (ret < 0) {
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dev_err(smbus->dev, "Timeout, status 0x%08x\n", status);
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return -ETIME;
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}
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}
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/* Controller timeout? */
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if (status & SMSTA_TOM) {
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dev_err(smbus->dev, "Controller timeout, status 0x%08x\n", status);
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return -EIO;
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}
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/* Peripheral timeout? */
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if (status & SMSTA_MTO) {
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dev_err(smbus->dev, "Peripheral timeout, status 0x%08x\n", status);
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return -ETIME;
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}
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/* Still stuck in a transaction? */
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if (status & SMSTA_XIP) {
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dev_err(smbus->dev, "Bus stuck, status 0x%08x\n", status);
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return -EIO;
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}
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/* Arbitration loss? */
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if (status & SMSTA_MTA) {
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dev_err(smbus->dev, "Arbitration loss, status 0x%08x\n", status);
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return -EBUSY;
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}
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/* Got NACK? */
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if (status & SMSTA_MTN) {
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dev_err(smbus->dev, "NACK, status 0x%08x\n", status);
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return -ENXIO;
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}
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/* Clear XEN */
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reg_write(smbus, REG_SMSTA, SMSTA_XEN);
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return 0;
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}
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static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
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struct i2c_msg *msg, int stop)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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int read, i, err;
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u32 rd;
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read = msg->flags & I2C_M_RD ? 1 : 0;
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TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg));
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if (read) {
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TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
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(stop ? MTXFIFO_STOP : 0));
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err = pasemi_smb_waitready(smbus);
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if (err)
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goto reset_out;
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for (i = 0; i < msg->len; i++) {
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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msg->buf[i] = rd & MRXFIFO_DATA_M;
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}
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} else {
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for (i = 0; i < msg->len - 1; i++)
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TXFIFO_WR(smbus, msg->buf[i]);
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TXFIFO_WR(smbus, msg->buf[msg->len-1] |
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(stop ? MTXFIFO_STOP : 0));
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if (stop) {
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err = pasemi_smb_waitready(smbus);
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if (err)
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goto reset_out;
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}
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}
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return 0;
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reset_out:
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pasemi_reset(smbus);
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return err;
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}
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static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs, int num)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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int ret, i;
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ret = pasemi_smb_clear(smbus);
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if (ret)
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return ret;
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for (i = 0; i < num && !ret; i++)
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ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
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return ret ? ret : num;
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}
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static int pasemi_smb_xfer(struct i2c_adapter *adapter,
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u16 addr, unsigned short flags, char read_write, u8 command,
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int size, union i2c_smbus_data *data)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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unsigned int rd;
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int read_flag, err;
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int len = 0, i;
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/* All our ops take 8-bit shifted addresses */
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addr <<= 1;
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read_flag = read_write == I2C_SMBUS_READ;
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err = pasemi_smb_clear(smbus);
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if (err)
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return err;
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switch (size) {
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case I2C_SMBUS_QUICK:
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TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
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MTXFIFO_STOP);
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break;
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case I2C_SMBUS_BYTE:
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TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
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if (read_write)
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TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
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else
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TXFIFO_WR(smbus, MTXFIFO_STOP | command);
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break;
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case I2C_SMBUS_BYTE_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
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} else {
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TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
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}
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break;
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case I2C_SMBUS_WORD_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
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} else {
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TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
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}
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break;
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case I2C_SMBUS_BLOCK_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
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rd = RXFIFO_RD(smbus);
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len = min_t(u8, (rd & MRXFIFO_DATA_M),
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I2C_SMBUS_BLOCK_MAX);
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TXFIFO_WR(smbus, len | MTXFIFO_READ |
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MTXFIFO_STOP);
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} else {
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len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
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TXFIFO_WR(smbus, len);
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for (i = 1; i < len; i++)
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TXFIFO_WR(smbus, data->block[i]);
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TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
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}
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break;
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case I2C_SMBUS_PROC_CALL:
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read_write = I2C_SMBUS_READ;
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
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break;
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case I2C_SMBUS_BLOCK_PROC_CALL:
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len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
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read_write = I2C_SMBUS_READ;
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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TXFIFO_WR(smbus, len);
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for (i = 1; i <= len; i++)
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TXFIFO_WR(smbus, data->block[i]);
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
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TXFIFO_WR(smbus, MTXFIFO_READ | 1);
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rd = RXFIFO_RD(smbus);
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len = min_t(u8, (rd & MRXFIFO_DATA_M),
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I2C_SMBUS_BLOCK_MAX - len);
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TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
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break;
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default:
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dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
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return -EINVAL;
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}
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err = pasemi_smb_waitready(smbus);
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if (err)
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goto reset_out;
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if (read_write == I2C_SMBUS_WRITE)
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return 0;
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switch (size) {
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case I2C_SMBUS_BYTE:
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case I2C_SMBUS_BYTE_DATA:
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->byte = rd & MRXFIFO_DATA_M;
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break;
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case I2C_SMBUS_WORD_DATA:
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case I2C_SMBUS_PROC_CALL:
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->word = rd & MRXFIFO_DATA_M;
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->word |= (rd & MRXFIFO_DATA_M) << 8;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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case I2C_SMBUS_BLOCK_PROC_CALL:
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data->block[0] = len;
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for (i = 1; i <= len; i ++) {
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->block[i] = rd & MRXFIFO_DATA_M;
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}
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break;
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}
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return 0;
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reset_out:
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pasemi_reset(smbus);
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return err;
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}
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static u32 pasemi_smb_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
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}
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static const struct i2c_algorithm smbus_algorithm = {
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.xfer = pasemi_i2c_xfer,
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.smbus_xfer = pasemi_smb_xfer,
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.functionality = pasemi_smb_func,
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};
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int pasemi_i2c_common_probe(struct pasemi_smbus *smbus)
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{
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int error;
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smbus->adapter.owner = THIS_MODULE;
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snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
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"PA Semi SMBus adapter (%s)", dev_name(smbus->dev));
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smbus->adapter.algo = &smbus_algorithm;
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smbus->adapter.algo_data = smbus;
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/* set up the sysfs linkage to our parent device */
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smbus->adapter.dev.parent = smbus->dev;
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smbus->use_irq = 0;
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init_completion(&smbus->irq_completion);
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if (smbus->hw_rev != PASEMI_HW_REV_PCI)
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smbus->hw_rev = reg_read(smbus, REG_REV);
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reg_write(smbus, REG_IMASK, 0);
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pasemi_reset(smbus);
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error = devm_i2c_add_adapter(smbus->dev, &smbus->adapter);
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if (error)
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return error;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pasemi_i2c_common_probe);
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irqreturn_t pasemi_irq_handler(int irq, void *dev_id)
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{
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struct pasemi_smbus *smbus = dev_id;
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|
reg_write(smbus, REG_IMASK, 0);
|
|
complete(&smbus->irq_completion);
|
|
return IRQ_HANDLED;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pasemi_irq_handler);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Olof Johansson <olof@lixom.net>");
|
|
MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
|