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80213934d0
FWSEC-FRTS is run with the desired address of the FRTS region as parameter, which we need to compute depending on some hardware parameters. Do this in a `FbLayout` structure, that will be later extended to describe more memory regions used to boot the GSP. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250619-nova-frts-v6-20-ecf41ef99252@nvidia.com [ In doc-comment of FbLayout s/bootup process/boot process/ - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
39 lines
1.1 KiB
Rust
39 lines
1.1 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::prelude::*;
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use crate::driver::Bar0;
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use crate::gpu::Chipset;
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mod ga100;
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mod ga102;
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mod tu102;
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pub(crate) trait FbHal {
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/// Returns the address of the currently-registered sysmem flush page.
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fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64;
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/// Register `addr` as the address of the sysmem flush page.
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///
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/// This might fail if the address is too large for the receiving register.
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fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result;
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/// Returns `true` is display is supported.
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fn supports_display(&self, bar: &Bar0) -> bool;
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/// Returns the VRAM size, in bytes.
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fn vidmem_size(&self, bar: &Bar0) -> u64;
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}
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/// Returns the HAL corresponding to `chipset`.
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pub(super) fn fb_hal(chipset: Chipset) -> &'static dyn FbHal {
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use Chipset::*;
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match chipset {
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TU102 | TU104 | TU106 | TU117 | TU116 => tu102::TU102_HAL,
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GA100 => ga100::GA100_HAL,
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GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => {
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ga102::GA102_HAL
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}
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}
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}
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