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69f5cd67ce
Booting the GSP on Ampere requires an intricate dance between the GSP and SEC2 falcons, where the GSP starts by running the FWSEC firmware to create the WPR2 region , and then SEC2 loads the actual RISC-V firmware into the GSP. Add the common Falcon code and HAL for Ampere GPUs, and instantiate the GSP and SEC2 Falcons that will be required to perform that dance and boot the GSP. Thanks to Ben Skeggs for pointing out an important bug in the memory scrubbing code that could lead to a race condition and ultimately a failure to boot the GSP! Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250619-nova-frts-v6-15-ecf41ef99252@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
24 lines
636 B
Rust
24 lines
636 B
Rust
// SPDX-License-Identifier: GPL-2.0
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use crate::{
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driver::Bar0,
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falcon::{Falcon, FalconEngine},
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regs,
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};
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/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
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pub(crate) struct Gsp(());
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impl FalconEngine for Gsp {
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const BASE: usize = 0x00110000;
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}
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impl Falcon<Gsp> {
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/// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
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/// allow GSP to signal CPU for processing new messages in message queue.
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pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
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regs::NV_PFALCON_FALCON_IRQSCLR::default()
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.set_swgen0(true)
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.write(bar, Gsp::BASE);
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}
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}
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