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32cb1cc358
This commit enables basic support for the GB100/GB102 Blackwell GPUs. Beyond HW class ID plumbing there's very little change here vs GH100. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "priv.h"
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#include <nvhw/drf.h>
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#include <nvhw/ref/gb100/dev_hshub_base.h>
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static void
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gb100_fb_sysmem_flush_page_init(struct nvkm_fb *fb)
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{
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const u32 addr_hi = upper_32_bits(fb->sysmem.flush_page_addr);
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const u32 addr_lo = lower_32_bits(fb->sysmem.flush_page_addr);
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const u32 hshub = DRF_LO(NV_PFB_HSHUB0);
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struct nvkm_device *device = fb->subdev.device;
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, addr_hi);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO, addr_lo);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI, addr_hi);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO, addr_lo);
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}
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static const struct nvkm_fb_func
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gb100_fb = {
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.sysmem.flush_page_init = gb100_fb_sysmem_flush_page_init,
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.vidmem.size = ga102_fb_vidmem_size,
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};
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int
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gb100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
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{
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return r535_fb_new(&gb100_fb, device, type, inst, pfb);
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}
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