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7c2d25f1e4
With minimal to no direct HW programming required, most nvkm_engine implementations are nearly identical when running on top of GSP-RM. Add a common implementation of the boilerplate, and use nvkm_rm_gpu to expose the correct class IDs. As they're now handled by common code, and there's no support for them prior to GSP-RM support - this deletes the GA100 NVDEC/NVJPG/OFA HALs, the GA102 NVENC/OFA HALs, and the AD102 GR/NVDEC/NVENC/NVJPG/OFA HALs. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
63 lines
2 KiB
C
63 lines
2 KiB
C
/*
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* Copyright 2021 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <subdev/gsp.h>
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static const struct nvkm_falcon_func
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ga102_nvdec_flcn = {
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.disable = gm200_flcn_disable,
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.enable = gm200_flcn_enable,
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.addr2 = 0x1c00,
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.reset_pmc = true,
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.reset_prep = ga102_flcn_reset_prep,
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.reset_wait_mem_scrubbing = ga102_flcn_reset_wait_mem_scrubbing,
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.imem_dma = &ga102_flcn_dma,
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.dmem_dma = &ga102_flcn_dma,
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};
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static const struct nvkm_nvdec_func
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ga102_nvdec = {
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.flcn = &ga102_nvdec_flcn,
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};
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static int
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ga102_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver, const struct nvkm_nvdec_fwif *fwif)
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{
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return 0;
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}
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static const struct nvkm_nvdec_fwif
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ga102_nvdec_fwif[] = {
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{ -1, ga102_nvdec_nofw, &ga102_nvdec },
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{}
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};
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int
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ga102_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_nvdec **pnvdec)
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{
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if (nvkm_gsp_rm(device->gsp))
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return -ENODEV;
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return nvkm_nvdec_new_(ga102_nvdec_fwif, device, type, inst, 0x848000, pnvdec);
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}
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