mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00

new drivers: - bring in the asahi uapi header standalone - nova-drm: stub driver rust dependencies (for nova-core): - auxiliary - bus abstractions - driver registration - sample driver - devres changes from driver-core - revocable changes core: - add Apple fourcc modifiers - add virtio capset definitions - extend EXPORT_SYNC_FILE for timeline syncobjs - convert to devm_platform_ioremap_resource - refactor shmem helper page pinning - DP powerup/down link helpers - remove disgusting turds - extended %p4cc in vsprintf.c to support fourcc prints - change vsprintf %p4cn to %p4chR, remove %p4cn - Add drm_file_err function - IN_FORMATS_ASYNC property - move sitronix from tiny to their own subdir rust: - add drm core infrastructure rust abstractions (device/driver, ioctl, file, gem) dma-buf: - adjust sg handling to not cache map on attach - allow setting dma-device for import - Add a helper to sort and deduplicate dma_fence arrays docs: - updated drm scheduler docs - fbdev todo update - fb rendering - actual brightness ttm: - fix delayed destroy resv object bridge: - add kunit tests - convert tc358775 to atomic - convert drivers to devm_drm_bridge_alloc - convert rk3066_hdmi to bridge driver scheduler: - add kunit tests panel: - refcount panels to improve lifetime handling - Powertip PH128800T004-ZZA01 - NLT NL13676BC25-03F, Tianma TM070JDHG34-00 - Himax HX8279/HX8279-D DDIC - Visionox G2647FB105 - Sitronix ST7571 - ZOTAC rotation quirk vkms: - allow attaching more displays i915: - xe3lpd display updates - vrr refactor - intel_display struct conversions - xe2hpd memory type identification - add link rate/count to i915_display_info - cleanup VGA plane handling - refactor HDCP GSC - fix SLPC wait boosting reference counting - add 20ms delay to engine reset - fix fence release on early probe errors xe: - SRIOV updates - BMG PCI ID update - support separate firmware for each GT - SVM fix, prelim SVM multi-device work - export fan speed - temp disable d3cold on BMG - backup VRAM in PM notifier instead of suspend/freeze - update xe_ttm_access_memory to use GPU for non-visible access - fix guc_info debugfs for VFs - use copy_from_user instead of __copy_from_user - append PCIe gen5 limitations to xe_firmware document amdgpu: - DSC cleanup - DC Scaling updates - Fused I2C-over-AUX updates - DMUB updates - Use drm_file_err in amdgpu - Enforce isolation updates - Use new dma_fence helpers - USERQ fixes - Documentation updates - SR-IOV updates - RAS updates - PSP 12 cleanups - GC 9.5 updates - SMU 13.x updates - VCN / JPEG SR-IOV updates amdkfd: - Update error messages for SDMA - Userptr updates - XNACK fixes radeon: - CIK doorbell cleanup nouveau: - add support for NVIDIA r570 GSP firmware - enable Hopper/Blackwell support nova-core: - fix task list - register definition infrastructure - move firmware into own rust module - register auxiliary device for nova-drm nova-drm: - initial driver skeleton msm: - GPU: - ACD (adaptive clock distribution) for X1-85 - drop fictional address_space_size - improve GMU HFI response time out robustness - fix crash when throttling during boot - DPU: - use single CTL path for flushing on DPU 5.x+ - improve SSPP allocation code for better sharing - Enabled SmartDMA on SM8150, SC8180X, SC8280XP, SM8550 - Added SAR2130P support - Disabled DSC support on MSM8937, MSM8917, MSM8953, SDM660 - DP: - switch to new audio helpers - better LTTPR handling - DSI: - Added support for SA8775P - Added SAR2130P support - HDMI: - Switched to use new helpers for ACR data - Fixed old standing issue of HPD not working in some cases amdxdna: - add dma-buf support - allow empty command submits renesas: - add dma-buf support - add zpos, alpha, blend support panthor: - fail properly for NO_MMAP bos - add SET_LABEL ioctl - debugfs BO dumping support imagination: - update DT bindings - support TI AM68 GPU hibmc: - improve interrupt handling and HPD support virtio: - add panic handler support rockchip: - add RK3588 support - add DP AUX bus panel support ivpu: - add heartbeat based hangcheck mediatek: - prepares support for MT8195/99 HDMIv2/DDCv2 anx7625: - improve HPD tegra: - speed up firmware loading -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmg2aVAACgkQDHTzWXnE hr6DjhAApr2fZjugU3EmpsARdcIWgEd+X65R97ef7RlUGqBKm2joSwZGOhH0oBsG 9WyO92Qzu6XMe8OibKqY4D2hir9UPz5v+uEWe3q9CzZGbNyAwyVRjVkaKpnI9upv 1dmHFI7HgPu6qbz6RfPIfgALBLXvVXMaQ4+ZgN/cLtZFa+OLAV5ByqWsRPPXZFb0 F/pQGQ4ursglfA+LH3SVPfnTN53lu93IlM5/Os9OQQGj+44w94zQ6DCm7CY1AugH n+RM/0Yv7WaoF1ByeOtq4FcrmLRrd+ozsvITbRZqhOx7zS/mhP8LRzAwgKWOYzSh puKunyQiSdHR7FSqSi8uyY3YumcLWNa/17LMKoTf+KqweJbKGE7RVBuFBn6WUdPb AYHZrSB4USAeyahdrrsU+q7ltu5urs5ckpbXsRurMiaUz/BLim1PIm3N5FDLPY7B PD1n1FcMUv3CmJT5Y+aNIQgmf1/dETESRTSAgSoOo3gNp6jdRCYqSuWIBsppibWT 26+tyz0/FGhE50QviHzg0Sv+jd/g93fN6snNlV8wNFMviq3bC69Toa+y3qJ5e7UC /42R7nCWdkCZJfr6E67rOaahe9TDV/LXLqPErwptOkdK8sMchaIgF+deybgTtTi/ zGRBfjLvb5ocYBmPbeGX4mtXNRpyZ3o9I0QUyGUO4zMwFXmFwn0= =jpVr -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iJUEABMJAB0WIQTkHFbLp4ejekA/qfgnX84Zoj2+dgUCaD7zuQAKCRAnX84Zoj2+ dv21AX4qAXMoS1eQQOzx5/MN0LhibwHO8lq0HgyhKKCMZTUvFP91hvuB6qKGzxEU +RJmN5cBgPGNuXwr9zLe5A/Lv1LWgfSj1DaAlauYvduFh1xyLOLuo0H3xfTsKrcl Onjxi5QVsg== =bMa5 -----END PGP SIGNATURE----- Merge drm-next-2025-05-28 into drm-misc-next Christian needs a recent drm-next branch to merge fence patches. Signed-off-by: Maxime Ripard <mripard@kernel.org>
482 lines
12 KiB
C
482 lines
12 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "chan.h"
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#include "chid.h"
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#include "cgrp.h"
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#include "runl.h"
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#include "priv.h"
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#include <core/ramht.h>
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#include <subdev/mmu.h>
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#include <engine/dma.h>
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#include <nvif/if0020.h>
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const struct nvkm_event_func
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nvkm_chan_event = {
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};
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void
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nvkm_chan_cctx_bind(struct nvkm_chan *chan, struct nvkm_engn *engn, struct nvkm_cctx *cctx)
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{
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struct nvkm_cgrp *cgrp = chan->cgrp;
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struct nvkm_runl *runl = cgrp->runl;
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struct nvkm_engine *engine = engn->engine;
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if (!engn->func->bind)
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return;
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CHAN_TRACE(chan, "%sbind cctx %d[%s]", cctx ? "" : "un", engn->id, engine->subdev.name);
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/* Prevent any channel in channel group from being rescheduled, kick them
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* off host and any engine(s) they're loaded on.
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*/
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if (cgrp->hw)
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nvkm_runl_block(runl);
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else
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nvkm_chan_block(chan);
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nvkm_chan_preempt(chan, true);
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/* Update context pointer. */
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engn->func->bind(engn, cctx, chan);
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/* Resume normal operation. */
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if (cgrp->hw)
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nvkm_runl_allow(runl);
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else
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nvkm_chan_allow(chan);
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}
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void
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nvkm_chan_cctx_put(struct nvkm_chan *chan, struct nvkm_cctx **pcctx)
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{
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struct nvkm_cctx *cctx = *pcctx;
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if (cctx) {
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struct nvkm_engn *engn = cctx->vctx->ectx->engn;
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if (refcount_dec_and_mutex_lock(&cctx->refs, &chan->cgrp->mutex)) {
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CHAN_TRACE(chan, "dtor cctx %d[%s]", engn->id, engn->engine->subdev.name);
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nvkm_cgrp_vctx_put(chan->cgrp, &cctx->vctx);
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list_del(&cctx->head);
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kfree(cctx);
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mutex_unlock(&chan->cgrp->mutex);
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}
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*pcctx = NULL;
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}
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}
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int
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nvkm_chan_cctx_get(struct nvkm_chan *chan, struct nvkm_engn *engn, struct nvkm_cctx **pcctx,
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struct nvkm_client *client)
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{
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struct nvkm_cgrp *cgrp = chan->cgrp;
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struct nvkm_vctx *vctx;
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struct nvkm_cctx *cctx;
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int ret;
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/* Look for an existing channel context for this engine+VEID. */
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mutex_lock(&cgrp->mutex);
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cctx = nvkm_list_find(cctx, &chan->cctxs, head,
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cctx->vctx->ectx->engn == engn && cctx->vctx->vmm == chan->vmm);
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if (cctx) {
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refcount_inc(&cctx->refs);
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*pcctx = cctx;
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mutex_unlock(&cgrp->mutex);
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return 0;
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}
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/* Nope - create a fresh one. But, sub-context first. */
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ret = nvkm_cgrp_vctx_get(cgrp, engn, chan, &vctx, client);
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if (ret) {
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CHAN_ERROR(chan, "vctx %d[%s]: %d", engn->id, engn->engine->subdev.name, ret);
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goto done;
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}
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/* Now, create the channel context - to track engine binding. */
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CHAN_TRACE(chan, "ctor cctx %d[%s]", engn->id, engn->engine->subdev.name);
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if (!(cctx = *pcctx = kzalloc(sizeof(*cctx), GFP_KERNEL))) {
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nvkm_cgrp_vctx_put(cgrp, &vctx);
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ret = -ENOMEM;
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goto done;
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}
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cctx->vctx = vctx;
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refcount_set(&cctx->refs, 1);
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refcount_set(&cctx->uses, 0);
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list_add_tail(&cctx->head, &chan->cctxs);
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done:
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mutex_unlock(&cgrp->mutex);
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return ret;
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}
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int
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nvkm_chan_preempt_locked(struct nvkm_chan *chan, bool wait)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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CHAN_TRACE(chan, "preempt");
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chan->func->preempt(chan);
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if (!wait)
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return 0;
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return nvkm_runl_preempt_wait(runl);
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}
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int
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nvkm_chan_preempt(struct nvkm_chan *chan, bool wait)
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{
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int ret;
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if (!chan->func->preempt)
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return 0;
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mutex_lock(&chan->cgrp->runl->mutex);
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ret = nvkm_chan_preempt_locked(chan, wait);
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mutex_unlock(&chan->cgrp->runl->mutex);
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return ret;
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}
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void
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nvkm_chan_remove_locked(struct nvkm_chan *chan)
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{
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struct nvkm_cgrp *cgrp = chan->cgrp;
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struct nvkm_runl *runl = cgrp->runl;
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if (list_empty(&chan->head))
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return;
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CHAN_TRACE(chan, "remove");
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if (!--cgrp->chan_nr) {
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runl->cgrp_nr--;
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list_del(&cgrp->head);
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}
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runl->chan_nr--;
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list_del_init(&chan->head);
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atomic_set(&runl->changed, 1);
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}
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void
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nvkm_chan_remove(struct nvkm_chan *chan, bool preempt)
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{
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struct nvkm_runl *runl = chan->cgrp->runl;
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mutex_lock(&runl->mutex);
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if (preempt && chan->func->preempt)
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nvkm_chan_preempt_locked(chan, true);
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nvkm_chan_remove_locked(chan);
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nvkm_runl_update_locked(runl, true);
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mutex_unlock(&runl->mutex);
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}
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void
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nvkm_chan_insert(struct nvkm_chan *chan)
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{
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struct nvkm_cgrp *cgrp = chan->cgrp;
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struct nvkm_runl *runl = cgrp->runl;
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mutex_lock(&runl->mutex);
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if (WARN_ON(!list_empty(&chan->head))) {
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mutex_unlock(&runl->mutex);
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return;
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}
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CHAN_TRACE(chan, "insert");
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list_add_tail(&chan->head, &cgrp->chans);
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runl->chan_nr++;
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if (!cgrp->chan_nr++) {
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list_add_tail(&cgrp->head, &cgrp->runl->cgrps);
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runl->cgrp_nr++;
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}
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atomic_set(&runl->changed, 1);
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nvkm_runl_update_locked(runl, true);
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mutex_unlock(&runl->mutex);
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}
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static void
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nvkm_chan_block_locked(struct nvkm_chan *chan)
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{
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CHAN_TRACE(chan, "block %d", atomic_read(&chan->blocked));
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if (atomic_inc_return(&chan->blocked) == 1)
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chan->func->stop(chan);
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}
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void
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nvkm_chan_error(struct nvkm_chan *chan, bool preempt)
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{
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unsigned long flags;
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spin_lock_irqsave(&chan->lock, flags);
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if (atomic_inc_return(&chan->errored) == 1) {
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CHAN_ERROR(chan, "errored - disabling channel");
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nvkm_chan_block_locked(chan);
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if (preempt)
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chan->func->preempt(chan);
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nvkm_event_ntfy(&chan->cgrp->runl->chid->event, chan->id, NVKM_CHAN_EVENT_ERRORED);
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}
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spin_unlock_irqrestore(&chan->lock, flags);
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}
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void
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nvkm_chan_block(struct nvkm_chan *chan)
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{
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spin_lock_irq(&chan->lock);
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nvkm_chan_block_locked(chan);
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spin_unlock_irq(&chan->lock);
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}
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void
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nvkm_chan_allow(struct nvkm_chan *chan)
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{
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spin_lock_irq(&chan->lock);
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CHAN_TRACE(chan, "allow %d", atomic_read(&chan->blocked));
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if (atomic_dec_and_test(&chan->blocked))
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chan->func->start(chan);
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spin_unlock_irq(&chan->lock);
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}
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void
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nvkm_chan_del(struct nvkm_chan **pchan)
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{
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struct nvkm_chan *chan = *pchan;
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if (!chan)
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return;
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if (chan->func->ramfc->clear)
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chan->func->ramfc->clear(chan);
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nvkm_ramht_del(&chan->ramht);
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nvkm_gpuobj_del(&chan->pgd);
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nvkm_gpuobj_del(&chan->eng);
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nvkm_gpuobj_del(&chan->cache);
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nvkm_gpuobj_del(&chan->ramfc);
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if (chan->cgrp) {
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nvkm_chid_put(chan->cgrp->runl->chid, chan->id, &chan->cgrp->lock);
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nvkm_cgrp_unref(&chan->cgrp);
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}
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nvkm_memory_unref(&chan->userd.mem);
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if (chan->vmm) {
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nvkm_vmm_part(chan->vmm, chan->inst->memory);
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nvkm_vmm_unref(&chan->vmm);
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}
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nvkm_gpuobj_del(&chan->push);
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nvkm_gpuobj_del(&chan->inst);
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kfree(chan);
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}
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void
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nvkm_chan_put(struct nvkm_chan **pchan, unsigned long irqflags)
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{
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struct nvkm_chan *chan = *pchan;
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if (!chan)
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return;
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*pchan = NULL;
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spin_unlock_irqrestore(&chan->cgrp->lock, irqflags);
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}
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struct nvkm_chan *
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nvkm_chan_get_inst(struct nvkm_engine *engine, u64 inst, unsigned long *pirqflags)
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{
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struct nvkm_fifo *fifo = engine->subdev.device->fifo;
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struct nvkm_runl *runl;
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struct nvkm_engn *engn;
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struct nvkm_chan *chan;
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nvkm_runl_foreach(runl, fifo) {
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nvkm_runl_foreach_engn(engn, runl) {
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if (engine == &fifo->engine || engn->engine == engine) {
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chan = nvkm_runl_chan_get_inst(runl, inst, pirqflags);
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if (chan || engn->engine == engine)
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return chan;
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}
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}
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}
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return NULL;
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}
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struct nvkm_chan *
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nvkm_chan_get_chid(struct nvkm_engine *engine, int id, unsigned long *pirqflags)
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{
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struct nvkm_fifo *fifo = engine->subdev.device->fifo;
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struct nvkm_runl *runl;
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struct nvkm_engn *engn;
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nvkm_runl_foreach(runl, fifo) {
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nvkm_runl_foreach_engn(engn, runl) {
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if (fifo->chid || engn->engine == engine)
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return nvkm_runl_chan_get_chid(runl, id, pirqflags);
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}
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}
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return NULL;
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}
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int
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nvkm_chan_new_(const struct nvkm_chan_func *func, struct nvkm_runl *runl, int runq,
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struct nvkm_cgrp *cgrp, const char *name, bool priv, u32 devm, struct nvkm_vmm *vmm,
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struct nvkm_dmaobj *dmaobj, u64 offset, u64 length,
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struct nvkm_memory *userd, u64 ouserd, struct nvkm_chan **pchan)
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{
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struct nvkm_fifo *fifo = runl->fifo;
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struct nvkm_device *device = fifo->engine.subdev.device;
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struct nvkm_chan *chan;
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int ret;
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/* Validate arguments against class requirements. */
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if ((runq && runq >= runl->func->runqs) ||
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(!func->inst->vmm != !vmm) ||
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(!func->userd->bar == !userd) ||
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(!func->ramfc->ctxdma != !dmaobj) ||
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((func->ramfc->devm < devm) && devm != BIT(0)) ||
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(!func->ramfc->priv && priv)) {
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RUNL_DEBUG(runl, "args runq:%d:%d vmm:%d:%p userd:%d:%p "
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"push:%d:%p devm:%08x:%08x priv:%d:%d",
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runl->func->runqs, runq, func->inst->vmm, vmm,
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func->userd->bar, userd, func->ramfc->ctxdma, dmaobj,
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func->ramfc->devm, devm, func->ramfc->priv, priv);
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return -EINVAL;
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}
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if (!(chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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chan->func = func;
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|
strscpy(chan->name, name, sizeof(chan->name));
|
|
chan->runq = runq;
|
|
chan->id = -1;
|
|
spin_lock_init(&chan->lock);
|
|
atomic_set(&chan->blocked, 1);
|
|
atomic_set(&chan->errored, 0);
|
|
INIT_LIST_HEAD(&chan->cctxs);
|
|
INIT_LIST_HEAD(&chan->head);
|
|
|
|
/* Join channel group.
|
|
*
|
|
* GK110 and newer support channel groups (aka TSGs), where individual channels
|
|
* share a timeslice, and, engine context(s).
|
|
*
|
|
* As such, engine contexts are tracked in nvkm_cgrp and we need them even when
|
|
* channels aren't in an API channel group, and on HW that doesn't support TSGs.
|
|
*/
|
|
if (!cgrp) {
|
|
ret = nvkm_cgrp_new(runl, chan->name, vmm, fifo->func->cgrp.force, &chan->cgrp);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "cgrp %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
cgrp = chan->cgrp;
|
|
} else {
|
|
if (cgrp->runl != runl || cgrp->vmm != vmm) {
|
|
RUNL_DEBUG(runl, "cgrp %d %d", cgrp->runl != runl, cgrp->vmm != vmm);
|
|
return -EINVAL;
|
|
}
|
|
|
|
chan->cgrp = nvkm_cgrp_ref(cgrp);
|
|
}
|
|
|
|
/* Allocate instance block. */
|
|
ret = nvkm_gpuobj_new(device, func->inst->size, 0x1000, func->inst->zero, NULL,
|
|
&chan->inst);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "inst %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
/* Initialise virtual address-space. */
|
|
if (func->inst->vmm) {
|
|
if (WARN_ON(vmm->mmu != device->mmu))
|
|
return -EINVAL;
|
|
|
|
ret = nvkm_vmm_join(vmm, chan->inst->memory);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "vmm %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
chan->vmm = nvkm_vmm_ref(vmm);
|
|
}
|
|
|
|
/* Allocate HW ctxdma for push buffer. */
|
|
if (func->ramfc->ctxdma) {
|
|
ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16, &chan->push);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "bind %d", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Allocate channel ID. */
|
|
chan->id = nvkm_chid_get(runl->chid, chan);
|
|
if (chan->id >= 0) {
|
|
if (!func->userd->bar) {
|
|
if (ouserd + chan->func->userd->size >=
|
|
nvkm_memory_size(userd)) {
|
|
RUNL_DEBUG(runl, "ouserd %llx", ouserd);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = nvkm_memory_kmap(userd, &chan->userd.mem);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "userd %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
chan->userd.base = ouserd;
|
|
} else {
|
|
chan->userd.mem = nvkm_memory_ref(fifo->userd.mem);
|
|
chan->userd.base = chan->id * chan->func->userd->size;
|
|
}
|
|
}
|
|
|
|
if (chan->id < 0) {
|
|
RUNL_ERROR(runl, "!chids");
|
|
return -ENOSPC;
|
|
}
|
|
|
|
if (cgrp->id < 0)
|
|
cgrp->id = chan->id;
|
|
|
|
/* Initialise USERD. */
|
|
if (chan->func->userd->clear)
|
|
chan->func->userd->clear(chan);
|
|
|
|
/* Initialise RAMFC. */
|
|
ret = chan->func->ramfc->write(chan, offset, length, devm, priv);
|
|
if (ret) {
|
|
RUNL_DEBUG(runl, "ramfc %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|