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6b252cf422
The new VM_BIND UAPI uses the DRM GPU VA manager to manage the VA space. Hence, we a need a way to manipulate the MMUs page tables without going through the internal range allocator implemented by nvkm/vmm. This patch adds a raw interface for nvkm/vmm to pass the resposibility for managing the address space and the corresponding map/unmap/sparse operations to the upper layers. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Danilo Krummrich <dakr@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230804182406.5222-11-dakr@redhat.com
117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
#ifndef __NVIF_IF000C_H__
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#define __NVIF_IF000C_H__
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struct nvif_vmm_v0 {
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__u8 version;
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__u8 page_nr;
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#define NVIF_VMM_V0_TYPE_UNMANAGED 0x00
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#define NVIF_VMM_V0_TYPE_MANAGED 0x01
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#define NVIF_VMM_V0_TYPE_RAW 0x02
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__u8 type;
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__u8 pad03[5];
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__u64 addr;
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__u64 size;
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__u8 data[];
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};
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#define NVIF_VMM_V0_PAGE 0x00
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#define NVIF_VMM_V0_GET 0x01
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#define NVIF_VMM_V0_PUT 0x02
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#define NVIF_VMM_V0_MAP 0x03
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#define NVIF_VMM_V0_UNMAP 0x04
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#define NVIF_VMM_V0_PFNMAP 0x05
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#define NVIF_VMM_V0_PFNCLR 0x06
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#define NVIF_VMM_V0_RAW 0x07
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#define NVIF_VMM_V0_MTHD(i) ((i) + 0x80)
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struct nvif_vmm_page_v0 {
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__u8 version;
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__u8 index;
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__u8 shift;
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__u8 sparse;
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__u8 vram;
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__u8 host;
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__u8 comp;
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__u8 pad07[1];
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};
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struct nvif_vmm_get_v0 {
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__u8 version;
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#define NVIF_VMM_GET_V0_ADDR 0x00
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#define NVIF_VMM_GET_V0_PTES 0x01
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#define NVIF_VMM_GET_V0_LAZY 0x02
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__u8 type;
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__u8 sparse;
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__u8 page;
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__u8 align;
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__u8 pad05[3];
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__u64 size;
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__u64 addr;
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};
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struct nvif_vmm_put_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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};
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struct nvif_vmm_map_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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__u64 size;
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__u64 memory;
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__u64 offset;
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__u8 data[];
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};
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struct nvif_vmm_unmap_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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};
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struct nvif_vmm_raw_v0 {
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__u8 version;
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#define NVIF_VMM_RAW_V0_GET 0x0
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#define NVIF_VMM_RAW_V0_PUT 0x1
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#define NVIF_VMM_RAW_V0_MAP 0x2
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#define NVIF_VMM_RAW_V0_UNMAP 0x3
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#define NVIF_VMM_RAW_V0_SPARSE 0x4
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__u8 op;
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__u8 sparse;
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__u8 ref;
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__u8 shift;
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__u32 argc;
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__u8 pad01[7];
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__u64 addr;
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__u64 size;
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__u64 offset;
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__u64 memory;
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__u64 argv;
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};
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struct nvif_vmm_pfnmap_v0 {
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__u8 version;
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__u8 page;
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__u8 pad02[6];
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__u64 addr;
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__u64 size;
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#define NVIF_VMM_PFNMAP_V0_ADDR 0xfffffffffffff000ULL
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#define NVIF_VMM_PFNMAP_V0_ADDR_SHIFT 12
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#define NVIF_VMM_PFNMAP_V0_APER 0x00000000000000f0ULL
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#define NVIF_VMM_PFNMAP_V0_HOST 0x0000000000000000ULL
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#define NVIF_VMM_PFNMAP_V0_VRAM 0x0000000000000010ULL
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#define NVIF_VMM_PFNMAP_V0_A 0x0000000000000004ULL
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#define NVIF_VMM_PFNMAP_V0_W 0x0000000000000002ULL
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#define NVIF_VMM_PFNMAP_V0_V 0x0000000000000001ULL
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#define NVIF_VMM_PFNMAP_V0_NONE 0x0000000000000000ULL
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__u64 phys[];
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};
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struct nvif_vmm_pfnclr_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 addr;
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__u64 size;
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};
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#endif
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