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b1ca384772
HOPPER_CHANNEL_GPFIFO_A removes the SEMAPHORE[A-D] methods that are currently used by nouveau to implement fences on GF100 and newer. Switch to the newer SEM methods available from VOLTA_CHANNEL_GPFIFO, which are also available on the Hopper/Blackwell host classes. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
93 lines
2 KiB
C
93 lines
2 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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#include "nv50_display.h"
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#include <nvif/push906f.h>
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#include <nvhw/class/clc36f.h>
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static int
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gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
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struct nvif_push *push = &chan->chan.push;
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int ret;
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ret = PUSH_WAIT(push, 8);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
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SEM_ADDR_HI, upper_32_bits(virtual),
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SEM_PAYLOAD_LO, sequence);
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PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
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NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |
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NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |
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NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
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NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
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PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
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PUSH_KICK(push);
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return 0;
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}
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static int
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gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
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struct nvif_push *push = &chan->chan.push;
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int ret;
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ret = PUSH_WAIT(push, 6);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
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SEM_ADDR_HI, upper_32_bits(virtual),
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SEM_PAYLOAD_LO, sequence);
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PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
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NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |
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NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |
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NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));
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PUSH_KICK(push);
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return 0;
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}
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static int
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gv100_fence_context_new(struct nouveau_channel *chan)
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{
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struct nv84_fence_chan *fctx;
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int ret;
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ret = nv84_fence_context_new(chan);
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if (ret)
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return ret;
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fctx = chan->fence;
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fctx->base.emit32 = gv100_fence_emit32;
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fctx->base.sync32 = gv100_fence_sync32;
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return 0;
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}
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int
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gv100_fence_create(struct nouveau_drm *drm)
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{
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struct nv84_fence_priv *priv;
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int ret;
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ret = nv84_fence_create(drm);
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if (ret)
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return ret;
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priv = drm->fence;
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priv->base.context_new = gv100_fence_context_new;
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return 0;
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}
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