mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
6cc6e08d45
Adds basic support for the new display classes available on GB20x GPUs. Most of the changes here deal with HW method moves, with the only other change of note being tweaks to skip allocation of CTXDMA objects, which aren't required on Blackwell display. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
297 lines
8.7 KiB
C
297 lines
8.7 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "head.h"
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#include "atom.h"
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#include "core.h"
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#include <nvif/pushc97b.h>
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#include <nvhw/class/clca7d.h>
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static int
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headca7d_display_id(struct nv50_head *head, u32 display_id)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_DISPLAY_ID(i, 0), display_id);
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return 0;
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}
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static int
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headca7d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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u8 depth;
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int ret;
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switch (asyh->or.depth) {
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case 6:
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depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444;
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break;
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case 5:
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depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444;
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break;
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case 2:
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depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444;
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break;
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case 0:
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depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444;
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break;
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default:
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WARN_ON(1);
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return -EINVAL;
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}
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
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NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE));
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return 0;
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}
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static int
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headca7d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_PROCAMP(i),
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NVDEF(NVCA7D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
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NVDEF(NVCA7D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |
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NVDEF(NVCA7D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA));
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return 0;
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}
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static int
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headca7d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_DITHER_CONTROL(i),
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NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
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NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
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NVDEF(NVCA7D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |
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NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
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NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
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return 0;
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}
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static int
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headca7d_curs_clr(struct nv50_head *head)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 4);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE));
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return 0;
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}
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static int
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headca7d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const u32 curs_hi = upper_32_bits(asyh->curs.offset);
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const u32 curs_lo = lower_32_bits(asyh->curs.offset);
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 7);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(i, 0), curs_hi);
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
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NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ADDRESS_LO, curs_lo >> 4) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
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NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0),
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HEAD_SET_CONTROL_CURSOR_COMPOSITION(i),
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NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,
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K1) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,
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NEG_K1_TIMES_SRC) |
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NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));
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return 0;
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}
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static int
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headca7d_olut_clr(struct nv50_head *head)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE));
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return 0;
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}
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static int
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headca7d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const u32 olut_hi = upper_32_bits(asyh->olut.offset);
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const u32 olut_lo = lower_32_bits(asyh->olut.offset);
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 6);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_OLUT(i), olut_hi,
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HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
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NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ADDRESS_LO, olut_lo >> 4) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_OLUT_CONTROL(i),
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NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) |
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NVDEF(NVCA7D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |
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NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |
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NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size),
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HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff);
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return 0;
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}
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static int
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headca7d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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struct nv50_head_mode *m = &asyh->mode;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 11);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_RASTER_SIZE(i),
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NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
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NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
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HEAD_SET_RASTER_SYNC_END(i),
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NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
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NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
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HEAD_SET_RASTER_BLANK_END(i),
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NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
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NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
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HEAD_SET_RASTER_BLANK_START(i),
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NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
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NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i),
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NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, PROGRESSIVE));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
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NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
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NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000));
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return 0;
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}
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static int
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headca7d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, 4);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN(i),
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NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
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NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
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PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
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NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
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NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH));
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return 0;
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}
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const struct nv50_head_func
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headca7d = {
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.view = headca7d_view,
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.mode = headca7d_mode,
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.olut = headc57d_olut,
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.ilut_check = head907d_ilut_check,
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.olut_identity = true,
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.olut_size = 1024,
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.olut_set = headca7d_olut_set,
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.olut_clr = headca7d_olut_clr,
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.curs_layout = head917d_curs_layout,
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.curs_format = headc37d_curs_format,
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.curs_set = headca7d_curs_set,
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.curs_clr = headca7d_curs_clr,
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.dither = headca7d_dither,
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.procamp = headca7d_procamp,
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.or = headca7d_or,
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.static_wndw_map = headc37d_static_wndw_map,
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.display_id = headca7d_display_id,
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};
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