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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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6cc6e08d45
Adds basic support for the new display classes available on GB20x GPUs. Most of the changes here deal with HW method moves, with the only other change of note being tweaks to skip allocation of CTXDMA objects, which aren't required on Blackwell display. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
98 lines
2.5 KiB
C
98 lines
2.5 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "crcc37d.h"
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#include "core.h"
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#include "head.h"
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#include <nvif/pushc97b.h>
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#include <nvhw/class/clca7d.h>
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static int
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crcca7d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int ret;
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ret = PUSH_WAIT(push, ctx ? 3 : 2);
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if (ret)
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return ret;
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if (ctx) {
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const u32 crc_hi = upper_32_bits(ctx->mem.addr);
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const u32 crc_lo = lower_32_bits(ctx->mem.addr);
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CRC(i), crc_hi,
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HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
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NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ADDRESS_LO, crc_lo >> 4) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE));
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} else {
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PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
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NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE));
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}
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return 0;
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}
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static int
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crcca7d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
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struct nv50_crc_notifier_ctx *ctx)
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{
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struct nvif_push *push = &head->disp->core->chan.push;
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const int i = head->base.index;
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int primary_crc, ret;
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if (!source) {
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ret = PUSH_WAIT(push, 1);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i), 0);
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return crcca7d_set_ctx(head, NULL);
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}
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switch (source) {
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case NV50_CRC_SOURCE_TYPE_SOR:
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primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(or);
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break;
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case NV50_CRC_SOURCE_TYPE_SF:
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primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF;
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break;
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default:
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break;
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}
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ret = crcca7d_set_ctx(head, ctx);
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if (ret)
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return ret;
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ret = PUSH_WAIT(push, 2);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i),
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NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
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NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
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NVVAL(NVCA7D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, primary_crc) |
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NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
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NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE));
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return 0;
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}
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const struct nv50_crc_func
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crcca7d = {
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.set_src = crcca7d_set_src,
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.set_ctx = crcca7d_set_ctx,
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.get_entry = crcc37d_get_entry,
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.ctx_finished = crcc37d_ctx_finished,
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.flip_threshold = CRCC37D_FLIP_THRESHOLD,
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.num_entries = CRCC37D_MAX_ENTRIES,
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.notifier_len = sizeof(struct crcc37d_notifier),
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};
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