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80dd5911cb
Add support for DSI on Qualcomm SM8750 SoC with notable difference: DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as parents before DSI PHY is configured, the PLLs are prepared and their initial rate is set. Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9(). Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/659619/ Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-7-a591c609743d@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
351 lines
12 KiB
C
351 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#include "dsi_cfg.h"
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static const char * const dsi_v2_bus_clk_names[] = {
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"core_mmss", "iface", "bus",
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};
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static const struct regulator_bulk_data apq8064_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */
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{ .supply = "avdd", .init_load_uA = 10000 }, /* 3.0 V */
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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};
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static const struct msm_dsi_config apq8064_dsi_cfg = {
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.io_offset = 0,
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.regulator_data = apq8064_dsi_regulators,
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.num_regulators = ARRAY_SIZE(apq8064_dsi_regulators),
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.bus_clk_names = dsi_v2_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
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.io_start = {
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{ 0x4700000, 0x5800000 },
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},
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};
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static const char * const dsi_6g_bus_clk_names[] = {
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"mdp_core", "iface", "bus", "core_mmss",
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};
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static const struct regulator_bulk_data msm8974_apq8084_regulators[] = {
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{ .supply = "vdd", .init_load_uA = 150000 }, /* 3.0 V */
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{ .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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};
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static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = msm8974_apq8084_regulators,
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.num_regulators = ARRAY_SIZE(msm8974_apq8084_regulators),
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.bus_clk_names = dsi_6g_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
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.io_start = {
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{ 0xfd922800, 0xfd922b00 },
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},
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};
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static const char * const dsi_v1_3_1_clk_names[] = {
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"mdp_core", "iface", "bus",
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};
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static const struct regulator_bulk_data dsi_v1_3_1_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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};
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static const struct msm_dsi_config msm8916_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = dsi_v1_3_1_regulators,
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.num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators),
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.bus_clk_names = dsi_v1_3_1_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names),
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.io_start = {
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{ 0x1a98000 },
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},
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};
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static const struct msm_dsi_config msm8976_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = dsi_v1_3_1_regulators,
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.num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators),
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.bus_clk_names = dsi_v1_3_1_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names),
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.io_start = {
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{ 0x1a94000, 0x1a96000 },
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},
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};
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static const struct regulator_bulk_data msm8994_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 100000 }, /* 1.25 V */
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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{ .supply = "vcca", .init_load_uA = 10000 }, /* 1.0 V */
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{ .supply = "vdd", .init_load_uA = 100000 }, /* 1.8 V */
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{ .supply = "lab_reg", .init_load_uA = -1 },
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{ .supply = "ibb_reg", .init_load_uA = -1 },
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};
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static const struct msm_dsi_config msm8994_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = msm8994_dsi_regulators,
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.num_regulators = ARRAY_SIZE(msm8994_dsi_regulators),
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.bus_clk_names = dsi_6g_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
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.io_start = {
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{ 0xfd998000, 0xfd9a0000 },
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},
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};
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static const struct regulator_bulk_data msm8996_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 18160 }, /* 1.25 V */
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{ .supply = "vcca", .init_load_uA = 17000 }, /* 0.925 V */
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{ .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */
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};
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static const struct msm_dsi_config msm8996_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = msm8996_dsi_regulators,
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.num_regulators = ARRAY_SIZE(msm8996_dsi_regulators),
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.bus_clk_names = dsi_6g_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
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.io_start = {
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{ 0x994000, 0x996000 },
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},
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};
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static const char * const dsi_msm8998_bus_clk_names[] = {
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"iface", "bus", "core",
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};
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static const struct regulator_bulk_data msm8998_dsi_regulators[] = {
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{ .supply = "vdd", .init_load_uA = 367000 }, /* 0.9 V */
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{ .supply = "vdda", .init_load_uA = 62800 }, /* 1.2 V */
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};
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static const struct msm_dsi_config msm8998_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = msm8998_dsi_regulators,
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.num_regulators = ARRAY_SIZE(msm8998_dsi_regulators),
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.bus_clk_names = dsi_msm8998_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
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.io_start = {
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{ 0xc994000, 0xc996000 },
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},
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};
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static const char * const dsi_sdm660_bus_clk_names[] = {
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"iface", "bus", "core", "core_mmss",
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};
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static const struct regulator_bulk_data sdm660_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 12560 }, /* 1.2 V */
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};
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static const struct msm_dsi_config sdm660_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = sdm660_dsi_regulators,
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.num_regulators = ARRAY_SIZE(sdm660_dsi_regulators),
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.bus_clk_names = dsi_sdm660_bus_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names),
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.io_start = {
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{ 0xc994000, 0xc996000 },
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},
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};
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static const char * const dsi_v2_4_clk_names[] = {
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"iface", "bus",
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};
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static const struct regulator_bulk_data dsi_v2_4_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */
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{ .supply = "refgen" },
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};
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static const struct msm_dsi_config sdm845_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = dsi_v2_4_regulators,
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.num_regulators = ARRAY_SIZE(dsi_v2_4_regulators),
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.bus_clk_names = dsi_v2_4_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
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.io_start = {
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{ 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
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{ 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */
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},
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};
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static const struct regulator_bulk_data sm8550_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 16800 }, /* 1.2 V */
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};
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static const struct msm_dsi_config sm8550_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = sm8550_dsi_regulators,
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.num_regulators = ARRAY_SIZE(sm8550_dsi_regulators),
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.bus_clk_names = dsi_v2_4_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
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.io_start = {
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{ 0xae94000, 0xae96000 },
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},
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};
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static const struct regulator_bulk_data sm8650_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 16600 }, /* 1.2 V */
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};
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static const struct msm_dsi_config sm8650_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = sm8650_dsi_regulators,
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.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
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.bus_clk_names = dsi_v2_4_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
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.io_start = {
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{ 0xae94000, 0xae96000 },
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},
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};
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static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */
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{ .supply = "refgen" },
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};
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static const struct msm_dsi_config sc7280_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = sc7280_dsi_regulators,
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.num_regulators = ARRAY_SIZE(sc7280_dsi_regulators),
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.bus_clk_names = dsi_v2_4_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
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.io_start = {
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{ 0xae94000, 0xae96000 },
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},
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};
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static const struct regulator_bulk_data sa8775p_dsi_regulators[] = {
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{ .supply = "vdda", .init_load_uA = 8300 }, /* 1.2 V */
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{ .supply = "refgen" },
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};
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static const struct msm_dsi_config sa8775p_dsi_cfg = {
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.io_offset = DSI_6G_REG_SHIFT,
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.regulator_data = sa8775p_dsi_regulators,
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.num_regulators = ARRAY_SIZE(sa8775p_dsi_regulators),
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.bus_clk_names = dsi_v2_4_clk_names,
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.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
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.io_start = {
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{ 0xae94000, 0xae96000 },
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},
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};
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static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
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.link_clk_set_rate = dsi_link_clk_set_rate_v2,
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.link_clk_enable = dsi_link_clk_enable_v2,
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.link_clk_disable = dsi_link_clk_disable_v2,
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.clk_init_ver = dsi_clk_init_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_v2,
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.tx_buf_get = dsi_tx_buf_get_v2,
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.tx_buf_put = NULL,
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.dma_base_get = dsi_dma_base_get_v2,
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.calc_clk_rate = dsi_calc_clk_rate_v2,
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};
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static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
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.link_clk_set_rate = dsi_link_clk_set_rate_6g,
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = NULL,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
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.link_clk_set_rate = dsi_link_clk_set_rate_6g,
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = dsi_clk_init_6g_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops = {
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.link_clk_set_rate = dsi_link_clk_set_rate_6g_v2_9,
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = dsi_clk_init_6g_v2_9,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
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{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
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&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
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&msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
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&msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
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&msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2,
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&msm8976_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0,
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&sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
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&msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_1,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
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&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_1,
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&sa8775p_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
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&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0,
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&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
|
|
&sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
|
|
};
|
|
|
|
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
|
|
{
|
|
const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
|
|
int i;
|
|
|
|
for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
|
|
if ((dsi_cfg_handlers[i].major == major) &&
|
|
(dsi_cfg_handlers[i].minor == minor)) {
|
|
cfg_hnd = &dsi_cfg_handlers[i];
|
|
break;
|
|
}
|
|
}
|
|
|
|
return cfg_hnd;
|
|
}
|