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e8cd8224a3
Set writeback encoders as possible clones for DSI encoders and vice versa. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/637498/ Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-14-a44c293cf422@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __DPU_ENCODER_H__
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#define __DPU_ENCODER_H__
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#include <drm/drm_crtc.h>
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#include "dpu_hw_mdss.h"
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#define DPU_ENCODER_FRAME_EVENT_DONE BIT(0)
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#define DPU_ENCODER_FRAME_EVENT_ERROR BIT(1)
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#define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2)
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#define DPU_ENCODER_FRAME_EVENT_IDLE BIT(3)
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#define IDLE_TIMEOUT (66 - 16/2)
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#define MAX_H_TILES_PER_DISPLAY 2
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/**
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* struct msm_display_info - defines display properties
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* @intf_type: INTF_ type
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* @num_of_h_tiles: Number of horizontal tiles in case of split interface
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* @h_tile_instance: Controller instance used per tile. Number of elements is
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* based on num_of_h_tiles
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* @is_cmd_mode Boolean to indicate if the CMD mode is requested
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* @vsync_source: Source of the TE signal for DSI CMD devices
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*/
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struct msm_display_info {
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enum dpu_intf_type intf_type;
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uint32_t num_of_h_tiles;
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uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
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bool is_cmd_mode;
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enum dpu_vsync_source vsync_source;
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};
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void dpu_encoder_assign_crtc(struct drm_encoder *encoder,
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struct drm_crtc *crtc);
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void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder,
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struct drm_crtc *crtc, bool enable);
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void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder);
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void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
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void dpu_encoder_kickoff(struct drm_encoder *encoder);
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int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time);
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int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder);
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int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder);
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enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder);
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void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder);
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uint32_t dpu_encoder_get_clones(struct drm_encoder *drm_enc);
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struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
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int drm_enc_mode,
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struct msm_display_info *disp_info);
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int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
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int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
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bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
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bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc);
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int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc);
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void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder);
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int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos);
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bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc);
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void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
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struct msm_display_topology *topology,
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struct drm_atomic_state *state,
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const struct drm_display_mode *adj_mode);
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bool dpu_encoder_needs_modeset(struct drm_encoder *drm_enc, struct drm_atomic_state *state);
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void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
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struct drm_writeback_job *job);
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void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
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struct drm_writeback_job *job);
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bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
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void dpu_encoder_start_frame_done_timer(struct drm_encoder *drm_enc);
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#endif /* __DPU_ENCODER_H__ */
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