linux/drivers/gpu/drm/i915/pxp/intel_pxp_regs.h
Alan Previn 5adacf19f6 drm/i915/pxp: Add MTL hw-plumbing enabling for KCR operation
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:

1. Updating 'pick-gt' to get the media tile for
   KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
   (init, status-checking, etc.).

While doing #2, lets create a separate registers header file for PXP
to be consistent with other i915 global subsystems.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230511231738.1077674-3-alan.previn.teres.alexis@intel.com
2023-05-11 17:26:25 -07:00

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C

/* SPDX-License-Identifier: MIT */
/*
* Copyright(c) 2023, Intel Corporation. All rights reserved.
*/
#ifndef __INTEL_PXP_REGS_H__
#define __INTEL_PXP_REGS_H__
#include "i915_reg_defs.h"
/* KCR subsystem register base address */
#define GEN12_KCR_BASE 0x32000
#define MTL_KCR_BASE 0x386000
/* KCR enable/disable control */
#define KCR_INIT(base) _MMIO((base) + 0xf0)
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
/* KCR hwdrm session in play status 0-31 */
#define KCR_SIP(base) _MMIO((base) + 0x260)
/* PXP global terminate register for session termination */
#define KCR_GLOBAL_TERMINATE(base) _MMIO((base) + 0xf8)
#endif /* __INTEL_PXP_REGS_H__ */