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fd585ee82c
Some display register files include i915_reg_defs.h, some don't include anything. Prefer intel_display_reg_defs.h in display. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://lore.kernel.org/r/06c24e1f6a7a2f6b4801b0a079eec3cc924402a7.1749469962.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/* Copyright © 2025 Intel Corporation */
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#ifndef __INTEL_SBI_REGS_H__
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#define __INTEL_SBI_REGS_H__
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#include "intel_display_reg_defs.h"
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/*
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* Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which
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* contains the register offset; and SBI_DATA, which contains the payload.
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*/
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#define SBI_ADDR _MMIO(0xC6000)
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#define SBI_ADDR_MASK REG_GENMASK(31, 16)
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#define SBI_ADDR_VALUE(addr) REG_FIELD_PREP(SBI_ADDR_MASK, (addr))
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#define SBI_DATA _MMIO(0xC6004)
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#define SBI_CTL_STAT _MMIO(0xC6008)
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#define SBI_CTL_DEST_MASK REG_GENMASK(16, 16)
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#define SBI_CTL_DEST_ICLK REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0)
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#define SBI_CTL_DEST_MPHY REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1)
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#define SBI_CTL_OP_MASK REG_GENMASK(15, 8)
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#define SBI_CTL_OP_IORD REG_FIELD_PREP(SBI_CTL_OP_MASK, 2)
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#define SBI_CTL_OP_IOWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 3)
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#define SBI_CTL_OP_CRRD REG_FIELD_PREP(SBI_CTL_OP_MASK, 6)
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#define SBI_CTL_OP_CRWR REG_FIELD_PREP(SBI_CTL_OP_MASK, 7)
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#define SBI_CTL_OP_WR REG_BIT(8)
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#define SBI_RESPONSE_MASK REG_GENMASK(2, 1)
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#define SBI_RESPONSE_FAIL REG_FIELD_PREP(SBI_RESPONSE_MASK, 1)
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#define SBI_RESPONSE_SUCCESS REG_FIELD_PREP(SBI_RESPONSE_MASK, 0)
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#define SBI_STATUS_MASK REG_GENMASK(0, 0)
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#define SBI_STATUS_BUSY REG_FIELD_PREP(SBI_STATUS_MASK, 1)
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#define SBI_STATUS_READY REG_FIELD_PREP(SBI_STATUS_MASK, 0)
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/* SBI offsets */
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#define SBI_SSCDIVINTPHASE 0x0200
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#define SBI_SSCDIVINTPHASE6 0x0600
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#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
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#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
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#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
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#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
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#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
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#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
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#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
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#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
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#define SBI_SSCDITHPHASE 0x0204
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#define SBI_SSCCTL 0x020c
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#define SBI_SSCCTL6 0x060C
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#define SBI_SSCCTL_PATHALT (1 << 3)
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#define SBI_SSCCTL_DISABLE (1 << 0)
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#define SBI_SSCAUXDIV6 0x0610
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#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
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#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
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#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
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#define SBI_DBUFF0 0x2a00
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#define SBI_GEN0 0x1f00
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#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
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#endif /* __INTEL_SBI_REGS_H__ */
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