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3c70ec71ab
By inspection, cxl_cper_handle_prot_err() is making a series of fragile
assumptions that can lead to crashes:
1/ It assumes that endpoints identified in the record are a CXL-type-3
device, nothing guarantees that.
2/ It assumes that the device is bound to the cxl_pci driver, nothing
guarantees that.
3/ Minor, it holds the device lock over the switch-port tracing for no
reason as the trace is 100% generated from data in the record.
Correct those by checking that the PCIe endpoint parents a cxl_memdev
before assuming the format of the driver data, and move the lock to where
it is required. Consequently this also makes the implementation ready for
CXL accelerators that are not bound to cxl_pci.
Fixes: 36f257e3b0 ("acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors")
Cc: Terry Bowman <terry.bowman@amd.com>
Cc: Li Ming <ming.li@zohomail.com>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Link: https://patch.msgid.link/20250612192043.2254617-1-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2025 AMD Corporation. All rights reserved. */
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#include <linux/pci.h>
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#include <linux/aer.h>
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#include <cxl/event.h>
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#include <cxlmem.h>
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#include "trace.h"
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static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
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trace_cxl_port_aer_correctable_error(&pdev->dev, status);
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}
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static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
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u32 fe;
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if (hweight32(status) > 1)
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fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
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ras_cap.cap_control));
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else
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fe = status;
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trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,
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ras_cap.header_log);
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}
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static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
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trace_cxl_aer_correctable_error(cxlmd, status);
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}
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static void
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cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
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u32 fe;
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if (hweight32(status) > 1)
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fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
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ras_cap.cap_control));
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else
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fe = status;
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trace_cxl_aer_uncorrectable_error(cxlmd, status, fe,
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ras_cap.header_log);
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}
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static int match_memdev_by_parent(struct device *dev, const void *uport)
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{
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if (is_cxl_memdev(dev) && dev->parent == uport)
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return 1;
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return 0;
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}
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static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
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{
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unsigned int devfn = PCI_DEVFN(data->prot_err.agent_addr.device,
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data->prot_err.agent_addr.function);
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struct pci_dev *pdev __free(pci_dev_put) =
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pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,
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data->prot_err.agent_addr.bus,
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devfn);
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struct cxl_memdev *cxlmd;
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int port_type;
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if (!pdev)
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return;
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port_type = pci_pcie_type(pdev);
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if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
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port_type == PCI_EXP_TYPE_DOWNSTREAM ||
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port_type == PCI_EXP_TYPE_UPSTREAM) {
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if (data->severity == AER_CORRECTABLE)
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cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);
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else
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cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);
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return;
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}
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guard(device)(&pdev->dev);
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if (!pdev->dev.driver)
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return;
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struct device *mem_dev __free(put_device) = bus_find_device(
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&cxl_bus_type, NULL, pdev, match_memdev_by_parent);
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if (!mem_dev)
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return;
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cxlmd = to_cxl_memdev(mem_dev);
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if (data->severity == AER_CORRECTABLE)
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cxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);
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else
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cxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);
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}
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static void cxl_cper_prot_err_work_fn(struct work_struct *work)
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{
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struct cxl_cper_prot_err_work_data wd;
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while (cxl_cper_prot_err_kfifo_get(&wd))
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cxl_cper_handle_prot_err(&wd);
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}
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static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
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int cxl_ras_init(void)
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{
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return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work);
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}
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void cxl_ras_exit(void)
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{
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cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work);
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cancel_work_sync(&cxl_cper_prot_err_work);
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}
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